index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
include
/
dt-bindings
/
clock
/
exynos4.h
Age
Commit message (
Expand
)
Author
Files
Lines
2018-10-05
dt-bindings: clock: samsung: Add SPDX license identifiers
Krzysztof Kozlowski
1
-5
/
+2
2018-10-05
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
Marek Szyprowski
1
-30
/
+0
2017-10-16
clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
Marek Szyprowski
1
-0
/
+35
2015-11-18
clk: samsung: exynos4: Add SSS gate clock
Krzysztof Kozlowski
1
-0
/
+1
2015-01-28
clk: samsung: exynos4: Add divider clock id for memory bus frequency
Chanwoo Choi
1
-1
/
+6
2014-09-22
clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
Marek Szyprowski
1
-0
/
+2
2014-09-22
clk: samsung: exynos4: add missing smmu_g2d clock and update comments
Marek Szyprowski
1
-5
/
+5
2014-07-26
clk: samsung: trivial: Correct typo in author's name
Tomasz Figa
1
-1
/
+1
2014-07-26
clk: samsung: exynos4: Add CLKOUT clock hierarchy
Tomasz Figa
1
-0
/
+5
2014-06-30
clk: exynos4: Add PPMU IP block source clocks.
Jonghwa Lee
1
-0
/
+18
2014-05-14
clk: samsung: exynos4: export sclk_hdmiphy clock
Tomasz Stanislawski
1
-0
/
+1
2014-05-14
clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocks
Sylwester Nawrocki
1
-1
/
+0
2014-01-08
ARM: exynos4: create a DT header defining CLK IDs
Andrzej Hajda
1
-0
/
+244