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path: root/include/dt-bindings/clock/aspeed-clock.h
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2022-08-26dt-bindings: clock: Add AST2500/AST2600 HACE reset definitionNeal Liu1-0/+1
Add HACE reset bit definition for AST2500/AST2600. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-11-01dt-bindings: clock: Add AST2500 RMII RCLK definitionsAndrew Jeffery1-0/+2
The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-07-06clk: aspeed: Fix SDCLK nameLei YU1-1/+1
The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-04Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-nextStephen Boyd1-0/+1
* clk-imx6sx: clk: imx6sl: correct ocram_podf clock type clk: imx6sx: disable unnecessary clocks during clock initialization clk: imx6sx: add missing lvds2 clock to the clock tree * clk-imx7d-enet: ARM: dts: imx7: correct enet ipg clock clk: imx7d: correct enet clock CCGR registers clk: imx7d: correct enet phy ref clock gates * clk-aspeed-24: clk: aspeed: Add 24MHz fixed clock
2018-06-01clk: aspeed: Add 24MHz fixed clockLei YU1-0/+1
Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by: Lei YU <mine260309@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-16clk:aspeed: Fix reset bits for PCI/VGA and PECIJae Hyun Yoo1-1/+1
This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules. 1. Reset bit for PCI/VGA is 8. 2. PECI reset bit is missing so added bit 10 as its reset bit. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Cc: stable <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-16clk: aspeed: Support second reset registerJoel Stanley1-0/+1
The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2017-12-21dt-bindings: clock: Add ASPEED constantsJoel Stanley1-0/+52
These will be used by the clock driver and device trees. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>