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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
include
/
dt-bindings
/
clk
Age
Commit message (
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Author
Files
Lines
2022-08-23
dt-bindings: clock: Move versaclock.h to dt-bindings/clock
Lukas Bulwahn
1
-13
/
+0
2022-08-23
dt-bindings: clock: Move lochnagar.h to dt-bindings/clock
Lukas Bulwahn
1
-26
/
+0
2020-06-23
dt: Add additional option bindings for IDT VersaClock
Adam Ford
1
-0
/
+13
2020-01-20
dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
Peter Ujfalusi
1
-40
/
+0
2019-02-07
mfd: lochnagar: Add initial binding documentation
Charles Keepax
1
-0
/
+26
2014-06-11
Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-...
Mike Turquette
1
-0
/
+40
2014-05-28
dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings
Peter Ujfalusi
1
-0
/
+40
2014-04-19
dt-bindings: clock: Move at91.h to dt-bindigs/clock
Tushar Behera
1
-22
/
+0
2014-03-20
dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
Tushar Behera
1
-26
/
+0
2014-01-24
Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turq...
Linus Torvalds
1
-1
/
+2
2014-01-08
clk: exynos-audss: add support for Exynos 5420
Andrew Bresticker
1
-1
/
+2
2013-12-02
clk: at91: add PMC macro file for dt definitions
Boris BREZILLON
1
-0
/
+22
2013-06-18
clk: samsung: register audio subsystem clocks using common clock framework
Padmavathi Venna
1
-0
/
+25