index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
include
/
asm-mips
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2008-04-28
[MIPS] Move arch/mips/philips to arch/mips/nxp
Daniel Laird
1
-1
/
+1
2008-04-28
[MIPS] Add support for MIPS CMP platform.
Ralf Baechle
1
-3
/
+4
2008-01-29
[MIPS] Alchemy: Au1210/Au1250 CPU support
Manuel Lauss
1
-2
/
+2
2007-10-12
[MIPS] Convert list of CPU types from #define to enum.
Ralf Baechle
1
-70
/
+49
2007-10-12
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
Ralf Baechle
1
-18
/
+17
2007-10-12
[MIPS] Add support for BCM47XX CPUs.
Aurelien Jarno
1
-2
/
+10
2007-07-10
[MIPS] PMC MSP71xx mips common
Marc St-Jean
1
-0
/
+2
2007-07-10
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Fuxin Zhang
1
-1
/
+6
2007-07-10
[MIPS] Enable support for the userlocal hardware register
Ralf Baechle
1
-0
/
+1
2007-07-06
[MIPS] Add macros to encode processor revisions.
Ralf Baechle
1
-0
/
+11
2006-07-14
[MIPS] Use the proper technical term for naming some of the cache macros.
Ralf Baechle
1
-1
/
+1
2006-06-01
[MIPS] Treat R14000 like R10000.
Kumba
1
-1
/
+3
2006-06-01
[MIPS] Fix detection and handling of the 74K processor.
Chris Dearman
1
-1
/
+3
2006-02-14
[MIPS] Fix CPU type bitmasks for MIPS III, IV and V.
Maciej W. Rozycki
1
-3
/
+3
2006-01-10
MIPS: Reorganize ISA constants strictly as bitmasks.
Ralf Baechle
1
-7
/
+10
2006-01-10
MIPS: Introduce machinery for testing for MIPSxxR1/2.
Ralf Baechle
1
-1
/
+3
2006-01-10
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Ralf Baechle
1
-10
/
+7
2005-10-29
Add support for SB1A CPU.
Andrew Isaacson
1
-1
/
+3
2005-10-29
Cleanup the mess in cpu_cache_init.
Ralf Baechle
1
-19
/
+21
2005-10-29
Move MIPS Technologies processor IDs to where they belong.
Maciej W. Rozycki
1
-2
/
+7
2005-10-29
Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.
Pete Popov
1
-1
/
+3
2005-10-29
Detect the MIPS R2 vectored interrupt, external interrupt controller
Ralf Baechle
1
-0
/
+4
2005-10-29
Detect the 34K.
Ralf Baechle
1
-1
/
+3
2005-10-29
Support the MIPS32 / MIPS64 DSP ASE.
Ralf Baechle
1
-0
/
+2
2005-10-29
Cleanup decoding of MIPSxx config registers.
Ralf Baechle
1
-1
/
+9
2005-10-29
Base Au1200 2.6 support.
Pete Popov
1
-1
/
+2
2005-10-29
Add a few more PrId vendor IDs.
Ralf Baechle
1
-6
/
+11
2005-04-17
Linux-2.6.12-rc2
Linus Torvalds
1
-0
/
+222