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2022-04-26v4l2: add pinctrl supportchanghuang.liang1-2/+3
2022-04-26v4l2: fixed sys_crg ioremap error!changhuang.liang1-3/+3
2022-04-26e24:driver: add e24 drever , use clk/rst api ,syscon spishanlong.li2-0/+3
add e24 drever, use clk/rst api, syscon spi Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-26mailbox:starfive: use clk/rst API.shanlong.li2-528/+516
1) use clk/rst api 2) fix coding style. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-25Merge branch 'CR_854_RTC_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu1-29/+59
rtc: starfive: Use stardand clock and reset apis for initialization See merge request sdk/sft-riscvpi-linux-5.10!30
2022-04-25Merge branch 'CR_853_TRNG_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu1-80/+94
Cr 853 trng hal.feng See merge request sdk/sft-riscvpi-linux-5.10!29
2022-04-25Merge branch 'CR_871_PWM_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu1-127/+152
Cr 871 pwm hal.feng See merge request sdk/sft-riscvpi-linux-5.10!28
2022-04-25rtc: starfive: Use stardand clock and reset apis for initializationHal Feng1-29/+59
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-25Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu1-77/+62
Cr 786 can clivia.cai See merge request sdk/sft-riscvpi-linux-5.10!24
2022-04-24hw_random: starfive-trng: Use stardand clock and reset apis for initializationHal Feng1-10/+44
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24hw_random: starfive-trng: Follow linux coding styleHal Feng1-70/+50
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24pwm: pwm-starfive-ptc: Use standard clock, reset, pinctrl framework for ↵Hal Feng1-11/+38
initialization Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24pwm: pwm-starfive-ptc: Follow linux coding styleHal Feng1-121/+119
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24risv:dts:starfive:Add timer clocktreexingyu.wu1-5/+5
1.Modify the clock tree driver to make timer clock ignore disabled_unused. 2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-04-24Merge branch 'CR_865_GMAC_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu2-19/+130
Cr 865 gmac yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!23
2022-04-24can:ipms_can: Driver code optimizationClivia.Cai1-77/+62
Use the syscon framework to manage the syscon registers. In addition, Use devm_reset_control_array_get_exclusive API to manage a list of reset controllers Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24PCI: plda: Add syscon register configmason.huo1-29/+91
Add the syscon register config when plda hw initializes. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add pcie clk & rstmason.huo1-1/+49
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Optimize plda pcie host drivermason.huo1-149/+147
Fix the hardcoded ATR setting. Fix some kernel coding standard issues. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24net:stmmac:dwc-qos: Add jh7110 supportyanhong.wang1-1/+130
The StarFive JH7110 SoC contains an instance of the Synopsys DWC ethernet QOS IP core.The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...). Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24net:stmmac: remove DWMAC_CORE_5_20 hw configyanhong.wang1-18/+0
The version DWMAC_CORE_5_20 and DWMAC_CORE_5_10 would use the same configuration,so remove the DWMAC_CORE_5_20 configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24Merge branch 'CR_881_DMA_curry.zhang' into 'jh7110_fpga_dev_5.15'andy.hu2-0/+17
[DMA] : Add standard system clock tree & reset API See merge request sdk/sft-riscvpi-linux-5.10!22
2022-04-24[DMA] : Add standard system clock tree & reset APIcurry.zhang2-0/+17
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-04-21arch:riscv:modify Kconfig.socsxingyu.wu1-1/+1
Kconfig.socs: remove the definitions like 'STARFIVE_BOARD_FPGA'. drivers:watchdog: change the definition. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19driver:watchdog:Add config definition to different uses of board levelxingyu.wu1-5/+7
1. The watchdog driver can get different rate from clock by different board. 2. arch:riscv:Kconfig: Adjust the format. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19driver:watchdog: Add clock & resetxingyu.wu1-18/+49
Add clock and reset in watchdog's driver and device tree. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19clk:starfive: Adjust the formatxingyu.wu6-526/+526
Adjust and modify the clock driver's format Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-19can:ipms_can: fix code styleClivia.Cai1-984/+670
Optimize the can driver code to conform to the upstream specification Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-19Merge branch 'CR_870_Reset_samin.guo' into 'jh7110_fpga_dev_5.15'andy.hu1-49/+60
Cr 870 reset samin.guo See merge request sdk/sft-riscvpi-linux-5.10!11
2022-04-19reset:starfive:jh7110: Macro definitions are rearranged in order.samin1-12/+9
Macro definitions are rearranged in order, for better coding style. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-19reset:starfive:jh7110: change how to obtain an assert addresssamin1-45/+59
Get assert addresses dynamically to reduce static array memory usage Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-15drivers:soc:starfive: support driver for starfive soc.samin2-0/+2
Add Kconfig/Makefile support for starfive soc. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-04-13modify pinctrl about vin_dvp function seljianlong.huang3-2/+21
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-13arch:riscv:Kconfig: Add choice with SOC board typexingyu.wu5-24/+26
Add config about user can choose the board type about FPGA, EVB or Visionfive Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add vout clock tree driverxingyu.wu4-0/+281
Clock references refer to include/dt-bindings/clock/starfive-jh7110-vout.h Change the value about 'status' of clkvout node in dts file when want to use vout clock. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-13clk:starfive: Add JH7110 clock tree driver for kernel 5.15xingyu.wu9-0/+1643
Add clock driver about sys, stg and aon clock for JH7110. Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-04-07enable pinctrl and modify gpio irq initjianlonghuang2-2/+53
Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com>
2022-04-07[pinctrl]Synchronize vic7100&jh7110 pinctrl subsystem“jenny.zhang”4-100/+42
2022-04-07[pinctrl] Update parse gpio dts node“jenny.zhang”1-8/+1
2022-04-07[pinctrl]Update gpio control code“jenny.zhang”3-192/+162
2022-04-07[pinctrl] 1.Update jh7110 pinctrl dts; 2.Adjust pinctrl coding style;“jenny.zhang”3-701/+734
2022-04-07[pinctrl] add jh7110 pinctrl dts and driver“jenny.zhang”7-0/+2069
2022-03-16rtc: starfive: Get the interrupt status using Completion.samin1-30/+45
starfiv rtc needs to get interrupt status when setting rtc clock and configuring hardware calibration. Use completion to identify states in interrupt handlers. In addition, when clearing the interrupt, you need to pull to determine whether to clear the state, otherwise the clearing will be unsuccessful. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-14riscv:uboot:starfive:dc8200keith.zhao48-2/+16227
update drdc8200iver kenerl version from 5.10 to 5.13 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2022-01-14soc:starfive: add jh7110 pmu driver.samin3-0/+338
The JH7110 PMU can dynamically switch on or off power domians and set the power-on and power-off sequence. API Instructions refer to include/soc/starfive/jh7110_pmu.h Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-131.add mailbox driver; 2.add mailbox test driver.shanlong.li4-0/+767
2022-01-12v4l2: add mipi pipeline suppport and ov13850 sensorchanghuang.liang7-30/+2163
2022-01-06[v4l2][update kernel5.15]david.li4-35/+32
2022-01-05reset: starfive-jh7110: Add isp/vout reset support.samin1-2/+30
Add isp/vout reset support for jh7110. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-01-05reset: starfive-jh7110: use platform_ioremap_iomem_byname.samin1-3/+17
The reset module is scattered in several domains, and each address segment may be located in the module device management. Using devm_platform_get_and_ioremap_resource->devm_ioremap_resource will cause the address of this segment to be occupied by the reset driver, and other modules cannot be used, so use ioremap that can be mapped multiple times instead. Signed-off-by: samin <samin.guo@starfivetech.com>
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