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2020-02-24drm/i915/gvt: Make WARN* drm specific where drm_priv ptr is availablePankaj Bharadiya8-13/+14
drm specific WARN* calls include device information in the backtrace, so we know what device the warnings originate from. Covert all the calls of WARN* with device specific drm_WARN* variants in functions where drm_i915_private struct pointer is readily available. The conversion was done automatically with below coccinelle semantic patch. checkpatch errors/warnings are fixed manually. @rule1@ identifier func, T; @@ func(...) { ... struct drm_i915_private *T = ...; <+... ( -WARN( +drm_WARN(&T->drm, ...) | -WARN_ON( +drm_WARN_ON(&T->drm, ...) | -WARN_ONCE( +drm_WARN_ONCE(&T->drm, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(&T->drm, ...) ) ...+> } @rule2@ identifier func, T; @@ func(struct drm_i915_private *T,...) { <+... ( -WARN( +drm_WARN(&T->drm, ...) | -WARN_ON( +drm_WARN_ON(&T->drm, ...) | -WARN_ONCE( +drm_WARN_ONCE(&T->drm, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(&T->drm, ...) ) ...+> } Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-8-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20drm/i915/gvt: make gvt oblivious of kvmgt data structuresJulian Stecklina2-135/+184
Instead of defining KVMGT per-device state in struct intel_vgpu directly, add an indirection. This makes the GVT code oblivious of what state KVMGT needs to keep. The intention here is to eventually make it possible to build hypervisor backends for the mediator, without having to touch the mediator itself. This is a first step. v2: - rebased onto gvt-staging (no conflicts) Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200217163858.26496-1-julian.stecklina@cyberus-technology.de
2020-02-20Merge drm-intel-next-queued into gvt-nextZhenyu Wang6482-159675/+354651
Backmerge to pull in https://patchwork.freedesktop.org/patch/353621/?series=73544&rev=1 Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2020-02-20drm/i915/dp: Add all tiled and port sync conns to modesetManasi Navare2-86/+135
If one of the synced crtcs needs a full modeset, we need to make sure all the synced crtcs are forced a full modeset. v3: * Remove ~BIT(cpu_trans) which is a nop (Ville) * use get_new_crtc_state and remove error check (Ville) v2: * Add tiles based on cpu_trans check (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214114126.13192-3-manasi.d.navare@intel.com
2020-02-20drm/i915/dp: Compute port sync crtc states post compute_config()Manasi Navare2-158/+108
This patch pushes out the computation of master and slave transcoders in crtc states after encoder's compute_config hook. This ensures that the assigned master slave crtcs have exact same mode and timings which is a requirement for Port sync mode to be enabled. v3: * Make crtc_state const, remove crtc state NULL init (Ville) v2: * Correct indentation * Rename to intel_ddi_port_sync_transcoders (Ville) * remove unwanted debug (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214114126.13192-2-manasi.d.navare@intel.com
2020-02-20drm/i915: Introduce encoder->compute_config_late()Ville Syrjälä2-0/+42
Add an optional secondary encoder state compute hook. This gets called after the normak .compute_config() has been called for all the encoders in the state. Thus in the new hook we can rely on all derived state populated by .compute_config() to be already set up. Should be useful for MST and port sync master/slave transcoder selection. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214114126.13192-1-manasi.d.navare@intel.com
2020-02-20drm/i915/gt: Do not attempt to reprogram IA/ring frequencies for dgfxChris Wilson2-11/+6
For dgfx, we do not need to reconfigure the IA/ring frequencies of the main processors as they are distinct devices. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219130119.1457693-1-chris@chris-wilson.co.uk
2020-02-19drm/i915/selftests: Mark GPR checking more hostileChris Wilson1-31/+96
Currently, we check that a new context has a clear set of general purpose registers. Add a little bit of hostility by preempting our new context and re-poisoning the GPR to ensure that there is no context leakage from preemption. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219123418.1447428-1-chris@chris-wilson.co.uk
2020-02-19drm/i915/selftest: Analyse timestamp behaviour across context switchesChris Wilson1-0/+229
Check that the CTX_TIMESTAMP is monotonic across context save/restore and upon preemption. References: https://gitlab.freedesktop.org/drm/intel/issues/1233 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219112004.1412791-1-chris@chris-wilson.co.uk
2020-02-19drm/i915: Read rawclk_freq earlierChris Wilson8-27/+35
Read the rawclk_freq during runtime info probing, prior to its first use in computing the CS timestamp frequency. Then store it in the runtime info, and include it in the debug printouts. Closes: https://gitlab.freedesktop.org/drm/intel/issues/834 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200216163445.555786-1-chris@chris-wilson.co.uk
2020-02-19drm/i915/gt: Refactor l3cc/mocs availabilityChris Wilson2-29/+67
On dgfx, we only use l3cc and not mocs, but we share the table containing both register definitions with Tigerlake. This confuses our selftest that verifies that both sets of registers do contain the values in our tables after various events (idling, reset, activity etc). When constructing the table of register definitions, also include the flags for which registers are valid so that information is computed centrally and available to all callers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Brian Welty <brian.welty@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-10-chris@chris-wilson.co.uk
2020-02-19drm/i915: split i915_driver_modeset_remove() to pre/post irq uninstallJani Nikula1-2/+9
Push irq uninstall further up, by splitting i915_driver_modeset_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214135058.7580-2-jani.nikula@intel.com
2020-02-19drm/i915: split intel_modeset_driver_remove() to pre/post irq uninstallJani Nikula3-7/+11
Split intel_modeset_driver_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. Move irq_unintall() closer to the layer it belongs. The error path in i915_driver_modeset_probe() looks obviously weird after this, but remains as good or broken as it ever was. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214135058.7580-1-jani.nikula@intel.com
2020-02-19drm/i915/gem: use spinlock_t instead of struct spinlockJani Nikula1-1/+1
spinlock_t is one case where the typedef is to be preferred over struct spinlock. Fixes: 42fb60de3129 ("drm/i915/gem: Don't leak non-persistent requests on changing engines") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200217184219.15325-1-jani.nikula@intel.com
2020-02-19drm/i915/gt: Show the cumulative context runtime in engine debugChris Wilson1-3/+5
As we have the total runtime known to us, show it when dumping the engine state for debug. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-2-chris@chris-wilson.co.uk
2020-02-19drm/i915/selftests: Flush tasklet on wait_for_submit()Chris Wilson1-4/+4
Always flush the tasklet if we have pending submissions in wait_for_submit(), so that even if we see the HW has started before we process its ack, when we return the execlists state is well defined. Fixes: 06289949b8dd ("drm/i915/selftests: Check for any sign of request starting in wait_for_submit()") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218211215.1336341-1-chris@chris-wilson.co.uk
2020-02-18drm/i915/gt: Fix up missing error propagation for heartbeat pulsesChris Wilson1-2/+6
Just missed setting err along an interruptible error path for the intel_engine_pulse(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-4-chris@chris-wilson.co.uk
2020-02-18drm/i915/selftests: Check for any sign of request starting in wait_for_submit()Chris Wilson1-1/+1
We only want to wait until the request has been submitted at least once; that is it is either in flight, or has been. References: fcf7df7aae24 ("drm/i915/selftests: Check for the error interrupt before we wait!") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218141305.1258394-1-chris@chris-wilson.co.uk
2020-02-18drm/i915/tgl: Add Wa_1808121037 to tgl.Rafael Antognolli1-0/+3
It's not clear whether this workaround is final yet, but the BSpec indicates that userspace needs to set bit 9 of this register on demand: "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501 Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> [mattrope: Tweaked comment while applying] Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212191728.25227-1-rafael.antognolli@intel.com
2020-02-18drm/i915/display: use intel_de_*() functions for register accessJani Nikula1-29/+38
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214140910.23194-2-jani.nikula@intel.com
2020-02-18drm/i915/csr: use intel_de_*() functions for register accessJani Nikula1-5/+6
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214140910.23194-1-jani.nikula@intel.com
2020-02-17drm/i915/selftests: Mark the mock ring->vma as being in the GGTTChris Wilson1-0/+3
The ringbuffer's vma is expected to be in the GGTT and that is now being checked, so make sure the mocked ring declares it so. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200215205927.4170144-1-chris@chris-wilson.co.uk
2020-02-17drm/i915/gt: Rearrange code to silence compilerChris Wilson1-3/+9
Without selftests enabled, I915_SELFTEST_ONLY becomes a dummy, generating a bare '0'. This causes the compiler to complain about a useless line, and while we could use I915_SELFTEST_DECLARE instead, it is a bit messier. Move the selftest-only code to a helper and make that conditional on having selftests enabled. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200217095835.599827-1-chris@chris-wilson.co.uk
2020-02-17drm/i915: switch vlv_suspend to use intel uncore register accessorsJani Nikula1-116/+121
Prefer intel_uncore_* over I915_READ, I915_WRITE, and POSTING_READ. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212144058.5686-2-jani.nikula@intel.com
2020-02-17drm/i915: split out vlv/chv specific suspend/resume codeJani Nikula5-489/+516
i915_drv.c is a fairly big file, and having very specific vlv/chv suspend/resume code in it is a distraction. Split it out to a new vlv_suspend.[ch] file. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212144058.5686-1-jani.nikula@intel.com
2020-02-17drm/i915: Update drm/i915 bug filing URLJani Nikula3-7/+6
We've moved from bugzilla to gitlab. Cc: stable@vger.kernel.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212160434.6437-2-jani.nikula@intel.com
2020-02-16drm/i915: Avoid potential division-by-zero in computing CS timestamp periodChris Wilson1-7/+11
Since we use a HW readback or estimation of the CS timestamp frequency, sometimes it may result in 0. Avoid the division-by-zero in computing its reciprocal, the timestamp period. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200216161746.500258-1-chris@chris-wilson.co.uk
2020-02-16drm/i915: Track hw reported context runtimeTvrtko Ursulin10-5/+195
GPU saves accumulated context runtime (in CS timestamp units) in PPHWSP which will be useful for us in cases when we are not able to track context busyness ourselves (like with GuC). Keep a copy of this in struct intel_context from where it can be easily read even if the context is not pinned. v2: (Chris) * Do not store pphwsp address in intel_context. * Log CS wrap-around. * Simplify calculation by relying on integer wraparound. v3: * Include total/avg in traces and error state for debugging Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200216133620.394962-1-chris@chris-wilson.co.uk
2020-02-15drm/i915: Force state->modeset=true when distrust_bios_wm==trueVille Syrjälä1-0/+14
Currently when we load the driver we set distrust_bios_wm=true, which will cause active_pipe_changes to get flagged even when we're not toggling any pipes on/off. The reason being that we want to fully redistribute the dbuf among the active pipes and ignore whatever state the firmware left behind. Unfortunately when the code flags active_pipe_changes it doesn't set state->modeset to true, which means the hardware dbuf state won't actually get updated. Hence the hardware and software states go out of sync, which can result in planes trying to use a disabled dbuf slice. Suprisingly that only seems to corrupt the display rather than making the whole display engine keel over. Let's fix this for now by flagging state->modeset whenever distrust_bios_wm is set. Eventually we'll likely want to rip out all of this mess and introduce proper statye tracking for dbuf. But that requires more work. Toss in a FIXME to that effect. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213140412.32697-4-stanislav.lisovskiy@intel.com
2020-02-15drm/i915/dsc: force full modeset whenever DSC is enabled at probeJani Nikula1-0/+18
We lack full state readout of DSC config, which may lead to DSC enable using a config that's all zeros, failing spectacularly. Force full modeset and thus compute config at probe to get a sane state, until we implement DSC state readout. Any fastset that did appear to work with DSC at probe, worked by coincidence. [1] is an example of a change that triggered the issue on TGL DSI DSC. [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org Fixes: fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support") Acked-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213140412.32697-3-stanislav.lisovskiy@intel.com
2020-02-15drm/i915: Ensure no conflicts with BIOS when updating DbufStanislav Lisovskiy1-2/+4
TGL BIOS seems to enable both DBuf slices ocasionally, depending how many displays are connected, while i915 according to BSpec was powering on S1 DBuf slice, until a modeset was done. This was causing a brief flash during the boot as we were disabling slice, previously used by BIOS with that. To prevent this, now we are ensuring tht we are enabling _at least_ one slice, but if there are more, let's not power them off. Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes") Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213140412.32697-2-stanislav.lisovskiy@intel.com
2020-02-15drm/i915/mst: Set intel_dp_set_m_n() for MST slavesJosé Roberto de Souza2-2/+5
Commit 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI platforms") moved the intel_dp_set_m_n() from hsw_crtc_enable() to intel_ddi_pre_enable_dp() but it missed add it to intel_mst_pre_enable_dp() causing MST slaves to not work. v2: Not setting intel_ddi_set_dp_msa() twice for MST master Fixes: 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI platforms") Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211185008.30806-1-jose.souza@intel.com
2020-02-14drm/i915/selftests: Check for the error interrupt before we wait!Chris Wilson1-0/+4
Sometimes the error interrupt can fire even before we have seen the request go active -- in which case, we end up waiting until the timeout as the request is already completed. Double check for this case! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214120659.3888735-1-chris@chris-wilson.co.uk
2020-02-14drm/i915: split out display debugfs to a separate fileJani Nikula8-2087/+2156
The i915_debugfs.c has grown more than a little unwieldy. Split out the display related debugfs code to a file of its own under display/, initialized with a separate call. No functional changes. v2: - Also moved i915_frontbuffer_tracking, i915_gem_framebuffer, i915_power_domain_info, i915_dmc_info, i915_ipc_status (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211161451.6867-2-jani.nikula@intel.com
2020-02-14drm/i915: move intel_csr.[ch] under display/Jani Nikula6-4/+4
The DMC firmware is about display. Move the handling under display. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211161451.6867-1-jani.nikula@intel.com
2020-02-14drm/i915: switch i915_driver_probe() to use i915 local variableJani Nikula1-27/+27
Prefer i915 over dev_priv where possible. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211162802.16180-2-jani.nikula@intel.com
2020-02-14drm/i915: register vga switcheroo later, unregister earlierJani Nikula1-10/+9
Move vga switcheroo and dsm handler register later in i915_driver_register(), and unregister in i915_driver_unregister(). The dsm handler unregister is a nop, and is only added for completeness. My unsubstantiated suspicion is that the vga switcheroo state change would not work as early as we register the hooks currently. In any case exposing the interfaces to the world only after we've got everything set up seems prudent. Also replace the error handling in vga switcheroo register with a simple error message. This is done at the same time due to lack of error propagation from i915_driver_register(). Cc: Lukas Wunner <lukas@wunner.de> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211162802.16180-1-jani.nikula@intel.com
2020-02-13drm/i915/hdmi: prefer to_i915() over drm->dev_private to get at i915Jani Nikula1-15/+10
drm->dev_private is to be avoided. Use to_i915() on the struct drm_device pointer instead. Rename the affected local dev_priv variables to i915 while at it. Cc: Wambui Karuga <wambui.karugax@gmail.com> Reviewed-by: Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211134427.31605-1-jani.nikula@intel.com
2020-02-13drm/i915/selftests: Exercise timeslice rewindingChris Wilson1-1/+214
Originally, I did not expect having to rewind a context upon timeslicing: the point was to replace the executing context with a non-executing one! However, given a second context that depends on requests from the first, we may have to split the requests along the first context to execute the second, causing us to partially replay the first context and so have to rewind its RING_TAIL. References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213140150.3639027-1-chris@chris-wilson.co.uk
2020-02-13drm/i915/gt: Suppress warnings for unused debugging localsChris Wilson1-2/+4
With debugging turned off, we have to tell the compiler not to warn about the unused debug locals. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213081217.3107410-1-chris@chris-wilson.co.uk
2020-02-13drm/i915: Use engine wa list for Wa_1607090982Mika Kuoppala1-3/+5
This is in mcr range of register, thus we can only verify it through mmio. Use engine wa list with mcr range verification skip. Fixes: 0db1a5f8706a ("drm/i915: Implement Wa_1607090982") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200212165707.11143-1-mika.kuoppala@linux.intel.com
2020-02-12drm/i915/gt: Expand bad CS completion event debugChris Wilson2-3/+31
Show the ring/request/context state if we see what we believe is an early CS completion. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211230944.1203098-1-chris@chris-wilson.co.uk
2020-02-12drm/i915/selftests: Avoid choosing zero for phys_szChris Wilson1-2/+4
Make sure we avoid ending up with a phys_sz of 0, or for phys_sz to be larger than the actual size. Closes: https://patchwork.freedesktop.org/series/73320/ Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212085432.1250807-1-chris@chris-wilson.co.uk
2020-02-12drm/i915/selftests: Sabotague the RING_HEADChris Wilson1-0/+79
Apply vast quantities of poison and not tell anyone to see if we fall for the trap of using a stale RING_HEAD. References: 42827350f75c ("drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211205615.1190127-2-chris@chris-wilson.co.uk
2020-02-12drm/i915: Poison rings after useChris Wilson1-9/+17
On retiring the request, we should not re-use these elements in the ring (at least not until we fill the ringbuffer and knowingly reuse the space). Leave behind some poison to (hopefully) trap ourselves if we make a mistake. Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211205615.1190127-1-chris@chris-wilson.co.uk
2020-02-12drm/i915/gem: Don't leak non-persistent requests on changing enginesChris Wilson4-13/+141
If we have a set of active engines marked as being non-persistent, we lose track of those if the user replaces those engines with I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that non-persistent requests are terminated if they are no longer being tracked by the user's context (in order to prevent a lost request causing an untracked and so unstoppable GPU hang), we need to apply the same context cancellation upon changing engines. v2: Track stale engines[] so we only reap at context closure. v3: Tvrtko spotted races with closing contexts and set-engines, so add a veneer of kill-everything paranoia to clean up after losing a race. Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional") Testcase: igt/gem_ctx_peristence/replace Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211144831.1011498-1-chris@chris-wilson.co.uk
2020-02-11drm/i915: Fix the docs for intel_set_cdclk_post_plane_update()Ville Syrjälä1-1/+1
s/before/after/ again after accidentally changing it the other way in commit 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200204154803.25403-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-02-11drm/i915: Don't use uninitialized 'ret'Ville Syrjälä1-4/+6
Accidentally removed the 'ret=0' initialization, and thus we're potentially looking at some stack garbage here. The whole 'ret = do_stuff; if (!ret) do_other_stuff;' pattern confuses my brain so let's replace it with the standard immediate return thing. Reported-by: Chris Wilson <chris@chris-wilson.co.uk> Fixes: 28a30b45f5e9 ("drm/i915: Convert cdclk to global state") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200207152228.1054-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2020-02-11drm/i915: Disable use of hwsp_cacheline for kernel_contextChris Wilson3-10/+30
Currently on execlists, we use a local hwsp for the kernel_context, rather than the engine's HWSP, as this is the default for execlists. However, seqno wrap requires allocating a new HWSP cacheline, and may require pinning a new HWSP page in the GGTT. This operation requiring pinning in the GGTT is not allowed within the kernel_context timeline, as doing so may require re-entering the kernel_context in order to evict from the GGTT. As we want to avoid requiring a new HWSP for the kernel_context, we can use the permanently pinned engine's HWSP instead. However to do so we must prevent the use of semaphores reading the kernel_context's HWSP, as the use of semaphores do not support rollover onto the same cacheline. Fortunately, the kernel_context is mostly isolated, so unlikely to give benefit to semaphores. Reported-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200210205722.794180-5-chris@chris-wilson.co.uk
2020-02-11drm/i915/selftests: Relax timeout for error-interrupt reset processingChris Wilson1-4/+11
We can not require that the system process a tasklet in reasonable time (thanks be to ksoftirqd), but we can insist that having waited sufficiently for the error interrupt to have been raised and having kicked the tasklet, the reset has begun and the request will be marked as in error (if not already completed). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200210205722.794180-3-chris@chris-wilson.co.uk
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-06 17:42:15 +0300