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2021-04-20hwmon: (ds1621) Use kobj_to_dev()Tian Tao1-1/+1
fixed the following coccicheck: ./drivers/hwmon/ds1621.c:329:60-61: WARNING opportunity for kobj_to_dev(). Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1616032504-59817-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (ftsteutates) Fix spelling typozuoqilin1-1/+1
Change 'revsion' to 'revision'. Signed-off-by: zuoqilin <zuoqilin@yulong.com> Link: https://lore.kernel.org/r/20210318124637.1331-1-zuoqilin1@163.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (corsair-psu) add support for critical valuesWilken Gottwalt1-55/+270
Adds support for reading the critical values of the temperature sensors and the rail sensors (voltage and current) once and caches them. Updates the naming of the constants following a more clear scheme. Also updates the documentation and fixes some typos. Updates is_visible and ops_read functions to be more readable. The new sensors output of a Corsair HX850i will look like this: corsairpsu-hid-3-1 Adapter: HID adapter v_in: 230.00 V v_out +12v: 12.14 V (crit min = +8.41 V, crit max = +15.59 V) v_out +5v: 5.03 V (crit min = +3.50 V, crit max = +6.50 V) v_out +3.3v: 3.30 V (crit min = +2.31 V, crit max = +4.30 V) psu fan: 0 RPM vrm temp: +46.2°C (crit = +70.0°C) case temp: +39.8°C (crit = +70.0°C) power total: 152.00 W power +12v: 108.00 W power +5v: 41.00 W power +3.3v: 5.00 W curr +12v: 9.00 A (crit max = +85.00 A) curr +5v: 8.31 A (crit max = +40.00 A) curr +3.3v: 1.62 A (crit max = +40.00 A) Signed-off-by: Wilken Gottwalt <wilken.gottwalt@posteo.net> Link: https://lore.kernel.org/r/YFNg6vGk3sQmyqgB@monster.powergraphx.local Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (pmbus/stpddc60) Add ST STPDDC60 pmbus driverErik Rosen3-0/+259
Add hardware monitoring support for ST STPDDC60 Unversal Digital Multicell Controller. Signed-off-by: Erik Rosen <erik.rosen@metormote.com> Link: https://lore.kernel.org/r/20210218115249.28513-3-erik.rosen@metormote.com [groeck: Fixed whitespace error in Makefile] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (pmbus) Add pmbus_set_update() function to set update flagErik Rosen2-0/+12
For the STPDDC60 chip, the vout alarm-limits are represented as an offset relative to the commanded output voltage. This means that the limits are dynamic and must not be cached by the pmbus driver. This patch adds a pmbus_set_sensor() function to pmbus_core to be able to set the update flag on selected sensors after auto-detection of limit attributes. Signed-off-by: Erik Rosen <erik.rosen@metormote.com> Link: https://lore.kernel.org/r/20210218115249.28513-2-erik.rosen@metormote.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (nct6683) Support NCT6686DJiqi Li1-2/+9
Add support for NCT6686D chip used in the Lenovo P620. Signed-off-by: Jiqi Li <lijq9@lenovo.com> Reviewed-by: Mark Pearson <markpearson@lenovo.com> Link: https://lore.kernel.org/r/20210304104421.1912934-1-lijq9@lenovo.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (pmbus) Add driver for Infineon IR36021Chris Packham3-0/+89
The IR36021 is a dual‐loop digital multi‐phase buck controller. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20210301035954.16713-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (corsair-psu) Update calculation of LINEAR11 valuesWilken Gottwalt1-22/+8
Changes the way how LINEAR11 values are calculated. The new method increases the precision of 2-3 digits. old method: corsairpsu-hid-3-1 Adapter: HID adapter v_in: 230.00 V v_out +12v: 12.00 V v_out +5v: 5.00 V v_out +3.3v: 3.00 V psu fan: 0 RPM vrm temp: +44.0°C case temp: +37.0°C power total: 152.00 W power +12v: 112.00 W power +5v: 38.00 W power +3.3v: 5.00 W curr in: N/A curr +12v: 9.00 A curr +5v: 7.00 A curr +3.3v: 1000.00 mA new method: corsairpsu-hid-3-1 Adapter: HID adapter v_in: 230.00 V v_out +12v: 12.16 V v_out +5v: 5.01 V v_out +3.3v: 3.30 V psu fan: 0 RPM vrm temp: +44.5°C case temp: +37.8°C power total: 148.00 W power +12v: 108.00 W power +5v: 37.00 W power +3.3v: 4.50 W curr in: N/A curr +12v: 9.25 A curr +5v: 7.50 A curr +3.3v: 1.50 A Co-developed-by: Jack Doan <me@jackdoan.com> Signed-off-by: Jack Doan <me@jackdoan.com> Signed-off-by: Wilken Gottwalt <wilken.gottwalt@posteo.net> Link: https://lore.kernel.org/r/YDoSMqFbgoTXyoru@monster.powergraphx.local Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: Switch to using the new API kobj_to_dev()Yang Li1-1/+1
fixed the following coccicheck: ./drivers/hwmon/hwmon.c:82:60-61: WARNING opportunity for kobj_to_dev() Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614071667-5665-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (adm9240) Convert to devm_hwmon_device_register_with_info APIGuenter Roeck1-495/+445
Also use regmap for register caching. This change reduces code and data size by more than 40%. While at it, fixed some warnings reported by checkpatch. Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (adm9240) Store i2c device instead of client in local dataGuenter Roeck1-15/+14
We only use the pointer to i2c_client to access &client->dev. Store the device pointer directly instead of retrieving it from i2c_client. Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20hwmon: (adm9240) Drop log messages from detect functionGuenter Roeck1-12/+5
Not detecting a chip in the detect function is normal and should not generate any log messages, much less error messages. Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2021-04-20Merge tag 'gvt-fixes-2021-04-20' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi1-6/+13
drm-intel-fixes gvt-fixes-2021-04-20 - Fix cmd parser regression on BDW (Zhenyu) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210420023312.GL1551@zhen-hp.sh.intel.com
2021-04-20PCI: Refactor HT advertising of NO_MSI flagMarc Zyngier1-11/+4
The few quirks that deal with NO_MSI tend to be copy-paste heavy. Refactor them so that the hierarchy of conditions is slightly cleaner. Link: https://lore.kernel.org/r/20210330151145.997953-15-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI/MSI: Document the various ways of ending up with NO_MSIMarc Zyngier1-2/+9
We have now three ways of ending up with NO_MSI being set. Document them. Link: https://lore.kernel.org/r/20210330151145.997953-14-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI: mediatek: Advertise lack of built-in MSI handlingThomas Gleixner1-0/+4
Some Mediatek host bridges cannot handle MSIs, which is sad. This also results in an ugly warning at device probe time, as the core PCI code wasn't told that MSIs were not available. Advertise this fact to the rest of the core PCI code by using the 'msi_domain' attribute, which still opens the possibility for another block to provide the MSI functionnality. [maz: commit message, switched over to msi_domain attribute] Link: https://lore.kernel.org/r/20210330151145.997953-13-maz@kernel.org Reported-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI/MSI: Make pci_host_common_probe() declare its reliance on MSI domainsMarc Zyngier1-0/+1
The generic PCI host driver relies on MSI domains for MSIs to be provided to its end-points. Make this dependency explicit. This cures the warnings occuring on arm/arm64 VMs when booted with PCI virtio devices and no MSI controller (no GICv3 ITS, for example). It is likely that other drivers will need to express the same dependency. Link: https://lore.kernel.org/r/20210330151145.997953-12-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI/MSI: Let PCI host bridges declare their reliance on MSI domainsMarc Zyngier1-0/+2
There is a whole class of host bridges that cannot know whether MSIs will be provided or not, as they rely on other blocks to provide the MSI functionnality, using MSI domains. This is the case for example on systems that use the ARM GIC architecture. Introduce a new attribute ('msi_domain') indicating that implicit dependency, and use this property to set the NO_MSI flag when no MSI domain is found at probe time. Link: https://lore.kernel.org/r/20210330151145.997953-11-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI/MSI: Kill default_teardown_msi_irqs()Marc Zyngier1-10/+1
It doesn't have any caller left. Link: https://lore.kernel.org/r/20210330151145.997953-10-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI/MSI: Drop use of msi_controller from core codeMarc Zyngier2-24/+1
As there is no driver using msi_controller, we can now safely remove its use from the PCI probe code. Link: https://lore.kernel.org/r/20210330151145.997953-8-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI: hv: Drop msi_controller structureMarc Zyngier1-4/+0
The Hyper-V PCI driver still makes use of a msi_controller structure, but it looks more like a distant leftover than anything actually useful, since it is initialised to 0 and never used for anything. Just remove it. Link: https://lore.kernel.org/r/20210330151145.997953-7-maz@kernel.org Tested-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI: xilinx: Convert to MSI domainsMarc Zyngier2-138/+106
In anticipation of the removal of the msi_controller structure, convert the ancient xilinx host controller driver to MSI domains. We end-up with the usual two domain structure, the top one being a generic PCI/MSI domain, the bottom one being xilinx-specific and handling the actual HW interrupt allocation. This allows us to fix some of the most appaling MSI programming, where the message programmed in the device is the virtual IRQ number instead of the allocated vector number. The allocator is also made safe with a mutex. This should allow support for MultiMSI, but I decided not to even try, since I cannot test it. Link: https://lore.kernel.org/r/20210330151145.997953-6-maz@kernel.org Tested-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI: xilinx: Don't allocate extra memory for the MSI capture addressMarc Zyngier1-12/+6
A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain an address that is fed to the controller as the MSI capture address (i.e. the MSI doorbell). But there is no actual requirement for this address to be RAM. All it needs to be is a suitable aligned address that will *not* be DMA'd to. Use the physical address of the 'port' data structure as the MSI capture address, aligned on a 4K boundary. Link: https://lore.kernel.org/r/20210330151145.997953-5-maz@kernel.org Tested-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2021-04-20PCI: rcar: Convert to MSI domainsMarc Zyngier2-183/+169
In anticipation of the removal of the msi_controller structure, convert the Rcar host controller driver to MSI domains. We end-up with the usual two domain structure, the top one being a generic PCI/MSI domain, the bottom one being Rcar-specific and handling the actual HW interrupt allocation. Link: https://lore.kernel.org/r/20210330151145.997953-4-maz@kernel.org Tested-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> [lorenzo.pieralisi@arm.com: merged fix https://lore.kernel.org/linux-pci/87y2e2p9wk.wl-maz@kernel.org] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20PCI: rcar: Don't allocate extra memory for the MSI capture addressMarc Zyngier1-11/+7
A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain an address that is fed to the controller as the MSI capture address (i.e. the MSI doorbell). But there is no actual requirement for this address to be RAM. All it needs to be is a suitable aligned address that will *not* be DMA'd to. Since the rcar platform already has a requirement that this address should be in the first 4GB of the physical address space, use the controller's own base address as the capture address. Link: https://lore.kernel.org/r/20210330151145.997953-3-maz@kernel.org Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2021-04-20PCI: tegra: Convert to MSI domainsMarc Zyngier2-159/+191
In anticipation of the removal of the msi_controller structure, convert the Tegra host controller driver to MSI domains. We end-up with the usual two domain structure, the top one being a generic PCI/MSI domain, the bottom one being Tegra-specific and handling the actual HW interrupt allocation. While at it, convert the normal interrupt handler to a chained handler, handle the controller's MSI IRQ edge triggered, support multiple MSIs per device and use the AFI_MSI_EN_VEC* registers to provide MSI masking. [treding@nvidia.com: fix, clean up and address TODOs from Marc's draft] Link: https://lore.kernel.org/r/20210330151145.997953-2-maz@kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20spi: stm32-qspi: Fix compilation warning in ARM64Patrice Chotard1-1/+1
This fixes warnings detected when compiling in ARM64. Introduced by 'commit 18674dee3cd6 ("spi: stm32-qspi: Add dirmap support")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210420082103.1693-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-04-20RDMA/mlx5: Fix type assignment for ICM DMMaor Gottlieb1-10/+13
We should hold the UAPI DM type in the base struct and not the internal mlx5 type. Fixes: 251b9d788750 ("RDMA/mlx5: Re-organize the DM code") Link: https://lore.kernel.org/r/58dedbd5c132660f808e59166d434e2eaa6ecf7a.1618753425.git.leonro@nvidia.com Signed-off-by: Maor Gottlieb <maorg@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-04-20IB/mlx5: Set right RoCE l3 type and roce version while deleting GIDParav Pandit2-6/+6
Currently when GID is deleted, it zero out all the fields of the RoCE address in the SET_ROCE_ADDRESS command for a specified index. roce_version = 0 means RoCEv1 in the SET_ROCE_ADDRESS command. This assumes that device has RoCEv1 always enabled which is not always correct. For example Subfunction does not support RoCEv1. Due to this assumption a previously added RoCEv2 GID is always deleted as RoCEv1 GID. This results in a below syndrome: mlx5_core.sf mlx5_core.sf.4: mlx5_cmd_check:777:(pid 4256): SET_ROCE_ADDRESS(0x761) op_mod(0x0) failed, status bad parameter(0x3), syndrome (0x12822d) Hence set the right RoCE version during GID deletion provided by the core. Link: https://lore.kernel.org/r/d3f54129c90ca329caf438dbe31875d8ad08d91a.1618753425.git.leonro@nvidia.com Signed-off-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-04-20RDMA/i40iw: Fix error unwinding when i40iw_hmc_sd_one failsSindhu Devale1-4/+2
When i40iw_hmc_sd_one fails, chunk is freed without the deletion of chunk entry in the PBLE info list. Fix it by adding the chunk entry to the PBLE info list only after successful addition of SD in i40iw_hmc_sd_one. This fixes a static checker warning reported here: https://lore.kernel.org/linux-rdma/YHV4CFXzqTm23AOZ@mwanda/ Fixes: 9715830157be ("i40iw: add pble resource files") Link: https://lore.kernel.org/r/20210416002104.323-1-shiraz.saleem@intel.com Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sindhu Devale <sindhu.devale@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-04-20RDMA/cxgb4: add missing qpid incrementPotnuri Bharat Teja1-1/+1
missing qpid increment leads to skipping few qpids while allocating QP. This eventually leads to adapter running out of qpids after establishing fewer connections than it actually supports. Current patch increments the qpid correctly. Fixes: cfdda9d76436 ("RDMA/cxgb4: Add driver for Chelsio T4 RNIC") Link: https://lore.kernel.org/r/20210415151422.9139-1-bharat@chelsio.com Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-04-20IB/ipoib: Remove unnecessary struct declarationWan Jiabing1-2/+0
struct ipoib_cm_tx is defined at 245th line. And the definition is independent on the MACRO. The declaration here is unnecessary. Remove it. Link: https://lore.kernel.org/r/20210415092124.27684-1-wanjiabing@vivo.com Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: Christoph Lameter <cl@linux.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-04-20dmaengine: idxd: remove detection of device typeDave Jiang6-75/+48
Move all static data type for per device type to an idxd_driver_data data structure. The data can be attached to the pci_device_id and provided by the pci probe function. This removes a lot of unnecessary type detection and setup code. Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852988924.2203940.2787590808682466398.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: iax bus removalDave Jiang4-87/+13
There is no need to have an additional bus for the IAX device. The removal of IAX will change user ABI as /sys/bus/iax will no longer exist. The iax device will be moved to the dsa bus. The device id for dsa and iax will now be combined rather than unique for each device type in order to accommodate the iax devices. This is in preparation for fixing the sub-driver code for idxd. There's no hardware deployment for Sapphire Rapids platform yet, which means that users have no reason to have developed scripts against this ABI. There is some exposure to released versions of accel-config, but those are being fixed up and an accel-config upgrade is reasonable to get IAX support. As far as accel-config is concerned IAX support starts when these devices appear under /sys/bus/dsa, and old accel-config just assumes that an empty / missing /sys/bus/iax just means a lack of platform support. Fixes: f25b463883a8 ("dmaengine: idxd: add IAX configuration support in the IDXD driver") Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852988298.2203940.4529909758034944428.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix cdev setup and free device lifetime issuesDave Jiang5-89/+63
The char device setup and cleanup has device lifetime issues regarding when parts are initialized and cleaned up. The initialization of struct device is done incorrectly. device_initialize() needs to be called on the 'struct device' and then additional changes can be added. The ->release() function needs to be setup via device_type before dev_set_name() to allow proper cleanup. The change re-parents the cdev under the wq->conf_dev to get natural reference inheritance. No known dependency on the old device path exists. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: 42d279f9137a ("dmaengine: idxd: add char driver to expose submission portal to userland") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/161852987721.2203940.1478218825576630810.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix group conf_dev lifetimeDave Jiang4-59/+88
Remove devm_* allocation and fix group->conf_dev 'struct device' lifetime. Address issues flagged by CONFIG_DEBUG_KOBJECT_RELEASE. Add release functions in order to free the allocated memory at the group->conf_dev destruction time. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852987144.2203940.8830315575880047.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix engine conf_dev lifetimeDave Jiang4-51/+86
Remove devm_* allocation and fix engine->conf_dev 'struct device' lifetime. Address issues flagged by CONFIG_DEBUG_KOBJECT_RELEASE. Add release functions in order to free the allocated memory at the engine conf_dev destruction time. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852986460.2203940.16603218225412118431.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix wq conf_dev 'struct device' lifetimeDave Jiang5-91/+146
Remove devm_* allocation and fix wq->conf_dev 'struct device' lifetime. Address issues flagged by CONFIG_DEBUG_KOBJECT_RELEASE. Add release functions in order to free the allocated memory for the wq context at device destruction time. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852985907.2203940.6840120734115043753.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix idxd conf_dev 'struct device' lifetimeDave Jiang3-90/+94
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Fix idxd->conf_dev 'struct device' lifetime. Address issues flagged by CONFIG_DEBUG_KOBJECT_RELEASE. Add release functions in order to free the allocated memory at the appropriate time. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852985319.2203940.4650791514462735368.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: use ida for device instance enumerationDave Jiang1-11/+6
The idr is only used for an device id, never to lookup context from that id. Switch to plain ida. Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161852984730.2203940.15032482460902003819.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: removal of pcim managed mmio mappingDave Jiang1-10/+23
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove pcim_* management of the PCI device and the ioremap of MMIO BAR and replace with unmanaged versions. This is for consistency of removing all the pcim/devm based calls. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/161852984150.2203940.8043988289748519056.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: cleanup pci interrupt vector allocation managementDave Jiang3-40/+30
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove devm managed pci interrupt vectors and replace with unmanged allocators. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/161852983563.2203940.8116028229124776669.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: fix dma device lifetimeDave Jiang3-18/+79
The devm managed lifetime is incompatible with 'struct device' objects that resides in idxd context. This is one of the series that clean up the idxd driver 'struct device' lifetime. Remove embedding of dma_device and dma_chan in idxd since it's not the only interface that idxd will use. The freeing of the dma_device will be managed by the ->release() function. Reported-by: Jason Gunthorpe <jgg@nvidia.com> Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/161852983001.2203940.14817017492384561719.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20Merge branch 'fixes' into nextVinod Koul10-51/+107
2021-04-20dmaengine: at_xdmac: Remove unused inline function at_xdmac_csize()YueHaibing1-11/+0
commit 765c37d87669 ("dmaengine: at_xdmac: rework slave configuration part") left behind this, so can remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20210407132543.23652-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dmaengine: idxd: Fix potential null dereference on pointer statusColin Ian King1-1/+2
There are calls to idxd_cmd_exec that pass a null status pointer however a recent commit has added an assignment to *status that can end up with a null pointer dereference. The function expects a null status pointer sometimes as there is a later assignment to *status where status is first null checked. Fix the issue by null checking status before making the assignment. Addresses-Coverity: ("Explicit null dereferenced") Fixes: 89e3becd8f82 ("dmaengine: idxd: check device state before issue command") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20210415110654.1941580-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20dt-bindings: dmaengine: qcom: gpi: add compatible for sm8150Felipe Balbi1-0/+1
No functional changes, just adding a new compatible for a diferent SoC. Signed-off-by: Felipe Balbi <felipe.balbi@microsoft.com> Link: https://lore.kernel.org/r/20210417061951.2105530-2-balbi@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-20PCI: Export pci_pio_to_address() for module useJianjun Wang1-0/+1
This interface will be used by PCI host drivers for PIO translation, export it to support compiling those drivers as kernel modules. Link: https://lore.kernel.org/r/20210420061723.989-3-jianjun.wang@mediatek.com Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-04-20Merge tag 'v5.12-rc8' into sched/core, to pick up fixesIngo Molnar801-3610/+6708
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2021-04-20thermal/drivers/tegra: Use devm_platform_ioremap_resource_bynamedingsenjie1-10/+3
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: dingsenjie <dingsenjie@yulong.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20210414063943.96244-1-dingsenjie@163.com
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-13 12:05:31 +0300