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2022-06-13DRM: use CONFIG_DRM_STARFIVE_MIPI_DSI change display channelVF_SDK_510_V1.1.2changhuang.liang2-1/+25
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: fixed mipi screen color errorchanghuang.liang2-2/+17
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add XR24 format supportchanghuang.liang2-0/+2
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drm: buffer flush l2cachechanghuang.liang3-1/+4
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13Update Kconfigchanghuang.liang1-1/+1
2022-06-13v4l2: change file authority to 0644changhuang.liang2-0/+0
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13V4L2: fix v4l2 coding stylechanghuang.liang20-166/+154
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13V4l2: add v4l2 drivers support!changhuang.liang30-3951/+17606
dts/starfive: add v4l2 configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/reset: add isp reset support!changhuang.liang3-1/+66
drivers/reset: modify reset-starfive-jh7100.c dts/satrfive: add isp resst support! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drivers/clk: add isp clk support!changhuang.liang3-0/+177
dts/starfive: add isp clk configure! Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: fixed drm register before i2c controllerchanghuang.liang8-197/+165
DRM: fixed hdmi color problem Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: open dsi transferchanghuang.liang1-1/+1
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: fixed nv21 format error!changhuang.liang1-3/+3
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add clk and reset apichanghuang.liang15-392/+336
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: delete printk debug logchanghuang.liang9-89/+7
m31: modify name "rx" to "tx" Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13fixed mipi screen errorchanghuang.liang4-2117/+7
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13drm: fixed coding stylechanghuang.liang17-2591/+2557
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13DRM: add drm driver supportchanghuang.liang27-1/+8231
dts/starfive: add drm driver configure Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in DMAxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13Audio: Add the new sampling rate for pwmdac drivercurry.zhang1-0/+0
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com> Author: curry.zhang <curry.zhang@starfivetech.com>
2022-06-13riscv: dts: starfive: Support AC108 daughter boardWalkerChenL2-1/+2
Add device tree support for AC108 daughter board, using the clock generated by Clock Tree. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in audio resetxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13reset: starfive: Add JH7100 audio reset driverEmil Renner Berthing5-11/+108
The audio resets are almost identical to the system resets, there are just fewer of them. So factor out and export a generic probe function, so most of the reset controller implementation can be shared. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100 in audio clkxingyu.wu1-1/+1
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-06-13clk: starfive: Add JH7100 audio clock driverEmil Renner Berthing2-0/+8
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13clk: starfive: jh7100: Handle audio_div clock properlyEmil Renner Berthing1-1/+53
It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dma/dw-axi-dmac/dw-axi-dmac-platform.c: fix building errojianlong.huang2-55/+16
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-06-13dmaengine: dw-axi-dmac-starfive: Remove calls specific to ARM64 ACPIGeert Uytterhoeven1-18/+2
iort_dma_setup() is being removed by commit db59e1b6e49201be ("ACPI: arm64: Move DMA setup operations out of IORT") in iommu/next: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_ do_memcpy’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration] 152 | iort_dma_setup(dma_dev, &dma_addr, &dma_size); | ^~~~~~~~~~~~~~ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 153 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 223 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64 ACPI implementation. As CONFIG_ACPI_IORT cannot be enabled on RISC-V, they were dummies anyway, so these calls can just be removed. [Emil: remove unused local variables too] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- Boot-tested, but the affected code paths were not exercised.
2022-06-13dmaengine: Add dw-axi-dmac-starfive driver for JH7100Tom2-10/+11
2022-06-13dmaengine: dw-axi-dmac: Add StarFive JH7100 supportSamin Guo2-20/+31
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dmaengine: dw-axi-dmac: Handle xfer start while non-idleSamin Guo1-1/+2
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2022-06-13dmaengine: dw-axi-dmac: Fix RMW on channel suspend registerEmil Renner Berthing1-3/+5
Found by comparing the parallel implementation of more than 8 channel support for the StarFive JH7100 SoC by Samin. Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Co-developed-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-06-13dmaengine: dw-axi-dmac: Fix uninitialized variable in ↵Tim Gardner1-2/+2
axi_chan_block_xfer_start() commit 885633075847f475f26a29249d772cc0da85d8cd upstream. Coverity complains of an uninitialized variable: 5. uninit_use_in_call: Using uninitialized value config.dst_per when calling axi_chan_config_write. [show details] 6. uninit_use_in_call: Using uninitialized value config.hs_sel_src when calling axi_chan_config_write. [show details] CID 121164 (#1-3 of 3): Uninitialized scalar variable (UNINIT) 7. uninit_use_in_call: Using uninitialized value config.src_per when calling axi_chan_config_write. [show details] 418 axi_chan_config_write(chan, &config); Fix this by initializing the structure to 0 which should at least be benign in axi_chan_config_write(). Also fix what looks like a cut-n-paste error when initializing config.hs_sel_dst. Fixes: 824351668a413 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Link: https://lore.kernel.org/r/20211025181656.31658-1-tim.gardner@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-13dmaengine: dw-axi-dmac: Simplify assignment in dma_chan_pause()Geert Uytterhoeven1-3/+2
commit 2f23355e96b4a5896de2032176197fa0c5c444dd upstream. Simplify assigning zero and performing a logical OR to a single assignment. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/r/2abd0da35608c14689a919d47dd45898a8ab4297.1635263478.git.geert@linux-m68k.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-13dmaengine: dw-axi-dmac: set coherent maskPandith N1-0/+4
commit 2d0f07f888f52532588730aae0241af5c5df393d upstream. Add support for setting dma coherent mask, dma mask is set to 64 bit Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-4-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-13dmaengine: dw-axi-dmac: Hardware handshake configurationPandith N1-0/+4
commit 93a7d32e9f4b8bad722a8c8c83c579a2f6a5aec3 upstream. Added hardware handshake selection in channel config, for mem2per and per2mem case. The peripheral specific handshake interface needs to be programmed in src_per, dst_per bits of CHx_CFG register. Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-3-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-13dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8Pandith N2-87/+122
commit 824351668a413af7d6d88e4ee2c9bee7c60daad2 upstream. Added support for DMA controller with more than 8 channels. DMAC register map changes based on number of channels. Enabling DMAC channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHENREG2 has to be used when number of channels > 8 Configuring DMA channel: CHx_CFG has to be used when number of channels <= 8 CHx_CFG2 has to be used when number of channels > 8 Suspending and resuming channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHSUSPREG has to be used for suspending a channel > 8 Signed-off-by: Pandith N <pandith.n@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-2-pandith.n@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-27pinctrl: starfive: Add mutex to lockVF_SDK_510_V1.0.2Jianlong Huang1-5/+23
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-04-27modify pwm to starfive adn modify serial interfacejianlong.huang2-2/+4
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-27serial: 8250_lpss: Extract dw8250_do_set_termios() for common useAndy Shevchenko4-10/+13
commit 7c4fc082f50431cc0814b47595ec9f9cca285993 upstream. Some of the code currently used in dw8250_set_termios(), byt_set_termios() may be reused by other methods in the future. Extract it to a common helper function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211005133026.21488-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-26add timer device and modify timer clk configjianlong.huang1-7/+7
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-26delete hwmon unless config and modify reset control interfacejianlong.huang2-19/+10
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-26spi: cadence-quadspi: Allow compilation on RISC-VEmil Renner Berthing1-1/+1
This IP is also used on the StarFive JH7100 riscv64 SoC and presumably also the upcoming JH7110 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-04-26drivers/pwm/pwm-sifive-ptc: Clear PWM CNTRyiming.li1-0/+4
Clear CNTR of PWM after setting period & duty_cycle
2022-04-26drivers/pwm: Add SiFive PWM PTC driverChenjieqin2-72/+54
2022-04-26watchdog: Add StarFive SI5 watchdog driverSamin Guo1-59/+53
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-04-21delete useless config to testjianlong.huang5-11/+1
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21disable starfive gpio and use pinctrljianlong.huang3-13/+4
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21modify interface different from kernel5.15jianlong.huang3-6/+6
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
2022-04-21modify SOC_STARFIVE macro to SOC_STARFIVE_VIC7100jianlong.huang7-11/+11
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 00:27:23 +0300