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2022-07-20Merge branch 'CR_1176_CLOCK_TREE_PLL_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou11-109/+944
CR 1176 clock tree pll xingyu.wu See merge request sdk/linux!280
2022-07-20watchdog:starfive:Update reset apixingyu.wu1-13/+7
Use 'devm_reset_control_array_get_exclusive' api to get reset controllers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify function format about 'jh7110_pll_data_from'xingyu.wu1-2/+2
Modify function format about 'jh7110_pll_data_from' Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Set PLL2 frequency when clock tree registeringxingyu.wu2-1/+14
In the file drivers/clk/starfive/clk-starfive-jh7110-pll.h, If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original. If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2 frequency will be set the new rate during clock tree registering. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL2 frequency controllerxingyu.wu4-25/+35
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL0 frequency controllerxingyu.wu7-2/+765
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, could read or set PLL0 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify the formatxingyu.wu7-110/+119
Modify the clocktree files' format Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20dt-bindings:clock:Delete external clock definitionsxingyu.wu5-0/+40
Move external clock definitions to C files that avoid illegal use. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20vout: fix failure problem of vout while startupshengyang.chen4-18/+7
fix failure problem of vout while startup Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-20Merge branch 'CR_1651_7110_evb_5.15_voutrst-1_shengyang.chen' into ↵Jason Zhou2-240/+20
'jh7110-5.15.y-devel' Cr 1651 7110 evb 5.15 voutrst 1 shengyang.chen See merge request sdk/linux!285
2022-07-20Merge branch 'CR_1562_SPI_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou1-2/+31
CR_1562 spi xingyu.wu See merge request sdk/linux!288
2022-07-20Merge branch 'CR_1560_v4l2_changhuang.liang' into 'jh7110-5.15.y-devel'Jason Zhou1-6/+1
CR_1560_v4l2_changhuang.liang See merge request sdk/linux!294
2022-07-20Merge branch 'CR_1631_7110_evb_5.15_mipitx_shengyang.chen' into ↵Jason Zhou2-23/+9
'jh7110-5.15.y-devel' CR_1631-5.15 riscv:linux:drm:mipitx See merge request sdk/linux!296
2022-07-20crypto:starfive: Switch CSR polling instead of interrupt for HMAC.jiajie.ho3-8/+4
Observed interrupt signal goes HIGH before HMAC calculations has been completed. Switching to use CSR polling to check for HMAC_DONE instead. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2022-07-20riscv:linux:drm:shengyang.chen2-23/+9
fix mipi shifted display problem remove useless process in vs_dc_hw.c Signed-off-by:shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-19spi:pl022-starfive:Turn off dma channel search under overlayxingyu.wu1-1/+4
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-07-19spi:pl022-starfive:Avoid power device error when CONFIG_PM enablexingyu.wu1-1/+27
It would be error when CONFIG_PM enable and use overlay by of-platform to register. And disable 'auto_runtime_pm' can be avoid. And add some power manager operation in platform probe function. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2022-07-19riscv:linux:drm:shengyang.chen2-240/+20
replace some reset interfaces for vout Signed-off-by:shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-18v4l2: fixed close wr due to system hungchanghuang.liang1-6/+1
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-14riscv:linux:vout:rgbkeith.zhao1-4/+4
Solve RGB channel display offset problem Signed-off-by: keith <keith.zhao@starfivetech.com>
2022-07-14rtc: starfive: Improve rtc driverHal Feng1-7/+28
1. Set initial time if rtc is never set. 2. Add timeout when clearing interrupt flag register. 3. Improve alarm function. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-14rtc: starfive: Improve coding styleHal Feng1-3/+6
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-12Merge branch 'CR_1458_timer_watchdog_wording_Xingyu.Wu' into ↵Jason Zhou5-192/+216
'jh7110-5.15.y-devel' CR 1458 timer watchdog wording xingyu.wu See merge request sdk/linux!269
2022-07-12Merge branch 'CR_1455_PCIe_Kevin.xie' into 'jh7110-5.15.y-devel'Jason Zhou1-1/+1
driver: pci: Add extended reset time for better compatibility See merge request sdk/linux!273
2022-07-12Merge branch 'CR_1537_USB_515_mason.huo' into 'jh7110-5.15.y-devel'Jason Zhou1-0/+12
usb: cdns3: Configuare phy as down-spread-spectrum See merge request sdk/linux!253
2022-07-12Merge branch 'CR_1480_7110_evb_5.15_mipitx_shengyang.chen' into ↵Jason Zhou2-3/+29
'jh7110-5.15.y-devel' riscv:linux:drm:mipidsi See merge request sdk/linux!265
2022-07-12Merge branch 'CR_1383_v4l2_pipeline_515_changhuang.liang' into ↵Jason Zhou12-458/+117
'jh7110-5.15.y-devel' v4l2: delete csiphy1 and csi1 subdev See merge request sdk/linux!255
2022-07-12Merge branch 'CR_1496_DRM_mipi_hdmi_colorIssue_keith.zhao' into ↵Jason Zhou1-6/+10
'jh7110-5.15.y-devel' riscv:driver:drm:DC8200 See merge request sdk/linux!271
2022-07-12Merge branch 'CR_1352_DRM_plane_overlay_515_Jack.Zhu' into 'jh7110-5.15.y-devel'Jason Zhou1-0/+8
[VOUT][DRM]fix redmine #1352: disable plane overlay in close flow See merge request sdk/linux!259
2022-07-12Merge branch 'CR_1427_I2C_hal.feng' into 'jh7110-5.15.y-devel'Jason Zhou1-1/+0
Cr 1427 i2c hal.feng See merge request sdk/linux!263
2022-07-12driver: pci: Add extended reset time for better compatibilityKevin.xie1-1/+1
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2022-07-12riscv:driver:drm:DC8200keith.zhao1-6/+10
1、fix issue #1496(#1320 is the same issue) Signed-off-by:keith.zhao <keith.zhao@statfivetech.com>
2022-07-12clocksource: starfive: Update timer namesLey Foon Tan2-3/+7
The existing implementation uses DT clock-names 'timer0', 'timer1' and etc as timer names. This will have issue if there are two timer instance IPs in the system. This patch update timer names to format below, example: timer@13050000.ch0 timer@13050000.ch1 timer@13050000.ch2 timer@13050000.ch3 Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2022-07-12clocksource: starfive: Add reset control supportxingyu.wu2-0/+21
Reset the timer if the reset control is available. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2022-07-12watchdog: starfive: Change "si5" to "starfive"Ley Foon Tan2-185/+185
Change all "si5" wording in driver to "starfive". No functional change. Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2022-07-12clocksource: starfive: Update compatible string to "starfive,timers"Ley Foon Tan1-2/+1
Update compatible string to "starfive,timers". Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2022-07-12clocksource: Kconfig: starfive: Update StarFive timer help descriptionLey Foon Tan1-2/+2
Same StarFive timer IP is used in JH8100 SoC. Remove JH71xx wording from description to be more generic. Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2022-07-11v4l2: modify bus_infochanghuang.liang1-1/+1
2022-07-11riscv:linux:drm:mipidsishengyang.chen2-3/+29
fix mipi display color problem Signed-off-by:shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-11drm: verisilicon: inno_hdmi: Fix an i2c failure during kernel startupHal Feng1-1/+0
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-08[VOUT][DRM]fix redmine #1352: disable plane overlay in close flowjack.zhu1-0/+8
2022-07-08Merge branch 'CR_1534_gpiomon_jianlong' into 'jh7110-5.15.y-devel'Jason Zhou1-0/+7
CR_1534 pinctrl: starfive: Fix gpiomon erro See merge request sdk/linux!249
2022-07-08Merge branch 'CR_1346_PWM_hal.feng' into 'jh7110-5.15.y-devel'Jason Zhou1-60/+45
Cr 1346 pwm hal.feng See merge request sdk/linux!257
2022-07-08pwm: pwm-starfive-ptc: Improve pwm accuracyHal Feng1-24/+38
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-08Merge branch 'CR_1490_7110_evb_5.15_mipitx_shengyang.chen' into ↵Jason Zhou1-0/+1
'jh7110-5.15.y-devel' riscv:linux:vout:m31 See merge request sdk/linux!250
2022-07-08usb: cdns3: Configuare phy as down-spread-spectrummason.huo1-0/+12
The default phy spread-spectrum mode is up-spread-spectrum, which is violated the usb3 spec. The up-spread-spectrum mode leads to phy buffers overrun. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-08v4l2: delete csiphy1 and csi1 subdevchanghuang.liang12-458/+117
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-08Merge branch 'CR_1311_CPUIdle_mason.huo' into 'jh7110-5.15.y-devel'andy.hu9-135/+903
Cr 1311 cpu idle mason.huo See merge request sdk/linux!247
2022-07-07riscv:linux:vout:m31shengyang.chen1-0/+1
fix 'NULL device' printing problem in console Signed-off-by:shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-07pinctrl: starfive: Fix gpiomon erroJianlong Huang1-0/+7
If enable CONFIG_PM, 'pm_runtime_get_sync' will return erro Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 02:48:25 +0300