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2022-02-25linux:driver:gpu:drm:starfiveSDK_v2.1.1SDK_v2.1.0yang1-0/+1
fix color problem of nv21 Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>
2022-02-10drm: Fix the crash issue when user space drm application use ↵andy.hu1-2/+1
drmPrimeFDToHandle method to import dmabuf from other module Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
2022-01-18Merge branch 'visionfive-5.15.y-devel' of ↵WalkerChenL1-23/+2
https://github.com/starfive-tech/linux into visionfive-5.15.y-devel
2022-01-18riscv: dts: starfive: Support AC108 daughter boardWalkerChenL2-1/+2
Add device tree support for AC108 daughter board, using the clock generated by Clock Tree. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-01-17riscv:linux:drivers:gpu:drm:starfiveshengyang.chen1-23/+2
DRM: Update README for configuring drm Signed-off-by: shengyang.chen <shengyang.chen@starfivetech.com>
2022-01-06riscv:driver:drm:starfive:mipi driverkJugg12-46/+1903
1. add mipi driver support in starfive drm 2. support build starfive drm as ko module Signed-off-by:kzhao<keith.zhao@statfivetech.com>
2022-01-04media/starfive: use clock and reset apiHal Feng12-82/+460
Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2022-01-04media/starfive: add starfive v4l2 driver frameworkHal Feng56-1/+27715
1. Add starfive video v4l2 driver framework 2. Support DVP sensor and MIPI csi sensor, eg: imx219, ov4689, dvp ov5640, sc2235 Signed-off-by: sw.multimedia <sw.multimedia@starfivetech.com> Signed-off-by: david.li <david.li@starfivetech.com> Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keithzhao <keith.zhao@starfivetech.com> Signed-off-by: andy.hu <andy.hu@starfivetech.com> Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2021-12-30drm/starfive: update clk configuration for lcdcMichaelZhuxx1-56/+5
Remove this part of the code that was originally intended for screen adaptation under the framebuffer framework, meanwhile, fix the problem that switching to some resolutions is not successful. Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
2021-12-29modify clock tree and support i2s audioWalker Chen3-14/+65
2021-12-26RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCsEmil Renner Berthing2-2/+2
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26spi: cadence-quadspi: Allow compilation on RISC-VEmil Renner Berthing1-1/+1
This IP is also used on the StarFive JH7100 riscv64 SoC and presumably also the upcoming JH7110 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26nvdla: Support compilation as moduleEmil Renner Berthing2-19/+20
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26nvdla: add NVDLA driverFarzad Farshchi33-0/+32586
Additional update from Prashant Gaikwad <pgaikwad@nvidia.com> Adapted for Linux 5.13 and the BeagleV Starlight board by <cybergaszcz@gmail.com>
2021-12-26drm/starfive: Propagate bridge error properlyEmil Renner Berthing1-2/+4
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26[WIP] drm/starfive: Support DRM_FORMAT_XRGB8888Emil Renner Berthing2-0/+2
When creating dumb buffers with 32bpp and 24bit colour depth this is default mode return by drm_mode_legacy_fb_format. So we need to support this for common dumb buffers to just work. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drm/starfive: Use actual clock rateEmil Renner Berthing1-1/+3
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drm/starfive: Use reset apiEmil Renner Berthing4-35/+30
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drm/starfive: Use clock apiEmil Renner Berthing4-13/+27
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drm/starfive: crtc: Use devm_platform_ioremap_resource_bynameEmil Renner Berthing3-33/+9
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drm/i2c/tda998x: Hardcode register values for Starlightsw.multimedia1-2/+5
A proper solution to this hack should be found. Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
2021-12-26drm/starfive: Add StarFive drm driversw.multimedia19-0/+3469
1. Add starfive DRM Display driver framework 2. Support M31 Phy and tda998x Signed-off-by: jack.zhu <jack.zhu@starfivetech.com> Signed-off-by: keith.zhao <keith.zhao@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26net: stmmac: use GFP_DMA32Matteo Croce1-4/+8
Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2021-12-26net: stmmac: Configure gtxclk based on speedTom1-0/+47
2021-12-26net: phy: motorcomm: Support the YT8521 gigabit PHYWalker Chen2-1/+449
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2021-12-26dmaengine: dw-axi-dmac-starfive: Remove calls specific to ARM64 ACPIGeert Uytterhoeven1-18/+2
iort_dma_setup() is being removed by commit db59e1b6e49201be ("ACPI: arm64: Move DMA setup operations out of IORT") in iommu/next: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_ do_memcpy’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration] 152 | iort_dma_setup(dma_dev, &dma_addr, &dma_size); | ^~~~~~~~~~~~~~ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 153 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’: drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 223 | iommu = iort_iommu_configure_id(dma_dev, NULL); | ^ iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64 ACPI implementation. As CONFIG_ACPI_IORT cannot be enabled on RISC-V, they were dummies anyway, so these calls can just be removed. [Emil: remove unused local variables too] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- Boot-tested, but the affected code paths were not exercised.
2021-12-26dmaengine: Add dw-axi-dmac-starfive driver for JH7100Tom5-0/+621
2021-12-26dmaengine: dw-axi-dmac: Add StarFive JH7100 supportSamin Guo2-1/+35
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Michael Scott <mike@foundries.io> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dmaengine: dw-axi-dmac: Handle xfer start while non-idleSamin Guo2-1/+13
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2021-12-26dmaengine: dw-axi-dmac: Fix RMW on channel suspend registerEmil Renner Berthing1-3/+5
Found by comparing the parallel implementation of more than 8 channel support for the StarFive JH7100 SoC by Samin. Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Co-developed-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26drivers/pwm/pwm-sifive-ptc: Clear PWM CNTRyiming.li1-0/+4
Clear CNTR of PWM after setting period & duty_cycle
2021-12-26drivers/pwm: Add SiFive PWM PTC driverChenjieqin3-0/+303
2021-12-26drivers/tty/serial/8250: update driver for JH7100Samin Guo1-0/+8
2021-12-26sifive/sifive_l2_cache: Align the address to cache lineAtish Patra1-0/+3
[Emil: fix suggested by Geert Uytterhoeven <geert@linux-m68k.org>] Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26sifive/sifive_l2_cache: Print a backtrace on out-of-range flushesGeert Uytterhoeven1-2/+2
This makes it easier to find out which driver passes a wrong address range. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-12-26sifive/sifive_l2_cache: Add disabling IRQ option (workaround)Tom3-0/+53
2021-12-26sifive/sifive_l2_cache: Add Starfive supportTom1-0/+1
2021-12-26sifive/sifive_l2_cache: Add sifive_l2_flush64_range functionTom2-1/+55
2021-12-26drivers/hw_random: Add StarFive JH7100 Random Number Generator driverHuan Feng4-0/+437
2021-12-26watchdog: Add StarFive SI5 watchdog driverSamin Guo3-0/+788
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2021-12-26hwmon: (sfctemp) Add StarFive JH7100 temperature sensorEmil Renner Berthing3-0/+360
Register definitions and conversion constants based on sfctemp driver by Samin in the StarFive 5.10 kernel. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2021-12-26serial: 8250_dw: Add quirk for starfive,jh7100-hsuart tooEmil Renner Berthing1-1/+3
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26pinctrl: starfive: Reset pinmux settingsEmil Renner Berthing1-0/+66
Current u-boot doesn't seem to take into account that some GPIOs are configured as inputs/outputs of certain peripherals on power-up. This means it ends up configuring some GPIOs as inputs to more than one peripheral which the documentation explicitly says is illegal. Similarly it also ends up configuring more than one GPIO as output of the same peripheral. While not explicitly mentioned by the documentation this also seems like a bad idea. The easiest way to remedy this mess is to just disconnect all GPIOs from peripherals and have our pinmux configuration set everything up properly. This, however, means that we'd disconnect the serial console from its pins for a while, so add a device tree property to keep certain GPIOs from being reset. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Keep more clocks aliveEmil Renner Berthing1-24/+24
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: starfive: Add JH7100 audio reset driverEmil Renner Berthing5-11/+108
The audio resets are almost identical to the system resets, there are just fewer of them. So factor out and export a generic probe function, so most of the reset controller implementation can be shared. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: starfive: Use 32bit I/O on 32bit registersEmil Renner Berthing1-20/+20
The driver currently uses 64bit I/O on the 32bit registers. This works because there are 4 assert registers and 4 status register, so they're only ever accessed on 64bit boundaries. There are however other reset controllers for audio and video on the SoC with only one status register that isn't 64bit aligned so 64bit I/O would result in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: Create subdirectory for StarFive driversEmil Renner Berthing5-8/+12
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: Add JH7100 audio clock driverEmil Renner Berthing3-0/+178
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Support more clock typesEmil Renner Berthing2-0/+41
Unlike the system clocks there are audio clocks that combine both multiplexer/divider and gate/multiplexer/divider, so add support for that. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Make hw clock implementation reusableEmil Renner Berthing2-89/+110
The JH7100 has additional audio and video clocks at different memory ranges, but they use the same register layout. Add a header and export the starfive_jh7100_clk_ops function so the clock implementation can be reused by drivers handling these clocks. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-26 18:24:15 +0300