summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2024-01-18drm/vs: simple encoderKeith Zhao4-1/+223
add simple encoder for dsi bridge Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2024-01-18drm/vs: Add hdmi driverKeith Zhao6-0/+1169
add hdmi driver as encoder and connect Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2024-01-18drm/vs: Add KMS crtc&planeKeith Zhao11-3/+3528
add 2 crtcs and 8 planes in vs-drm Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2024-01-18drm/vs: Register DRM deviceKeith Zhao8-0/+429
Implement drm device registration interface Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add TODO fileJack Zhu1-0/+4
Add a TODO.txt file to explain what needs to be done to get them out of staging. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Register devicesJack Zhu1-1/+96
Register ISP sub-device and video devices for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add interrupt handlingJack Zhu1-0/+21
Parse interrupt resources and register interrupt handlers. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add capture driverJack Zhu4-0/+693
Add capture driver for StarFive Camera Subsystem. It contains two video devices: capture_yuv and capture_raw. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add ISP driverJack Zhu5-0/+1260
Add ISP driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add video driverJack Zhu3-1/+674
Add video driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18media: staging: media: starfive: camss: Add core driverJack Zhu8-0/+485
Add core driver for StarFive Camera Subsystem. The code parses the device platform resources and registers related devices. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-18pmdomain: starfive: Update prefixes for AON power domainChanghuang Liang1-2/+2
Use "JH7110_AON_PD_" prefix for AON power doamin for JH7110 SoC. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20230927130734.9921-3-changhuang.liang@starfivetech.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18pmdomain: starfive: Move Kconfig file to the pmdomain subsystemUlf Hansson3-1/+2
The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Walker Chen <walker.chen@starfivetech.com> Cc: Conor Dooley <conor@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18pmdomain: Prepare to move Kconfig files into the pmdomain subsystemUlf Hansson2-0/+6
Rather than having the various Kconfig files for the genpd providers sprinkled across subsystems, let's prepare to move them into the pmdomain subsystem along with the implementations. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18pmdomain: starfive: Add JH7110 AON PMU supportChanghuang Liang1-5/+52
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the dphy rx/tx power switch. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230913-dude-imprecise-fc32622bc947@spud Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18pmdomain: starfive: Extract JH7110 pmu private operationsChanghuang Liang1-27/+62
Move JH7110 private operation into private data of compatible. Convenient to add AON PMU which would not have interrupts property. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230913-slideshow-luckiness-38ff17de84c6@spud Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18pmdomain: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEChanghuang Liang1-2/+2
Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230913-legibly-treachery-567cffcb5604@spud Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-18PCI: starfive: Add JH7110 PCIe controllerMinda Chen4-1/+556
Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 with PLDA host PCIe core. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Co-developed-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
2024-01-18PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time valueKevin Xie1-0/+16
Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum waiting time between exit from a conventional reset and sending the first configuration request to the device. As described in PCI base specification r6.0, section 6.6.1 <Conventional Reset>, there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2024-01-18PCI: plda: Add host init/deinit and map bus functionsMinda Chen2-14/+139
Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function. So vendor can use it to init PLDA PCIe host core. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
2024-01-18pci: plda: Add event bitmap field to struct plda_pcie_rpMinda Chen3-2/+6
For PLDA DMA interrupts are not all implemented. The non-implemented interrupts should be masked. So add a bitmap field to mask the non- implemented interrupts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-01-18PCI: microchip: Move IRQ functions to pcie-plda-host.cMinda Chen3-467/+475
Move IRQ related functions to pcie-plda-host.c for re-use these codes. Now Refactoring codes complete. Including MSI, INTx, event interrupts and IRQ init functions. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add event irqchip field to host port and add PLDA irqchipMinda Chen2-2/+69
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt controller. Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add get_events() callback and add PLDA get_event()Minda Chen2-1/+66
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt controller. PolarFire implements its own PCIe interrupts, additional to the regular PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA regular interrupts, necessitating a custom get_events() implementation. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... plda_get_events() adds interrupt register to PLDA local event num mapping codes. All The PLDA interrupts can be seen in new added graph. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add INTx and MSI event num to struct plda_eventMinda Chen2-2/+6
The INTx and MSI interrupt event num is different in Microchip and StarFive platform. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add request_event_irq() callback functionMinda Chen2-4/+32
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt controller. Microchip Polarfire PCIe add some PCIe interrupts base on PLDA IP interrupt controller. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... Both codes of register interrupts and mc_event_handler() contain additional interrupts symbol names, these can not be re-used. So add a new plda_event_handler() functions, which implements PLDA interrupt defalt handler. Add request_event_irq() callback function to compat Microchip Polorfire PCIe additional interrupts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add num_events field to struct plda_pcie_rpMinda Chen2-3/+6
The number of events is different across platforms. In order to share interrupt processing code, add a variable that defines the number of events so that it can be set per-platform instead of hardcoding it. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Rename interrupt related functionsMinda Chen1-52/+57
Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data instances. MSI, INTx interrupt code and IRQ init code are all can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Move setup functions to pcie-plda-host.cMinda Chen5-59/+84
Move setup functions to common pcie-plda-host.c. So these two functions can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Change the argument of plda_pcie_setup_iomems()Minda Chen1-3/+3
If other vendor do not select PCI_HOST_COMMON, the driver data is not struct pci_host_bridge. Move calling platform_get_drvdata() to mc_platform_init(). Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Rename two setup functionsMinda Chen1-12/+12
Rename two setup functions to plda prefix. Prepare to re-use these two setup function. For two setup functions names are similar, rename mc_pcie_setup_windows() to plda_pcie_setup_iomems(). Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Move PCIe host data structures to plda-pcie.hMinda Chen2-20/+21
Move the common data structures definition to head file for these two data structures can be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Rename two PCIe data structuresMinda Chen1-43/+53
Add PLDA PCIe related data structures by rename data structure name from mc_* to plda_*. axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. The event interrupt codes is still using struct mc_pcie because the event interrupt codes can not be re-used. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Add bridge_addr field to struct mc_pcieMinda Chen1-14/+9
For bridge address base is common PLDA field, Add this to struct mc_pcie first. INTx and MSI codes interrupts codes will get the bridge base address from port->bridge_addr. These codes will be changed to common codes. axi_base_addr is Microchip its own data. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Move PLDA IP register macros to pcie-plda.hMinda Chen2-92/+124
Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and local IRQ event number. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18PCI: microchip: Move pcie-microchip-host.c to plda directoryMinda Chen5-10/+19
For Microchip Polarfire PCIe host is PLDA XpressRich IP, move to plda directory. Prepare for refactoring the codes. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-01-18hwrng: starfive - Add runtime pm opsJia Jie Ho1-2/+6
Define SET_RUNTIME_PM_OPS for StarFive TRNG driver. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - Fix dev_err_probe return errorJia Jie Ho1-1/+1
Current dev_err_probe will return 0 instead of proper error code if driver failed to get irq number. Fix the return code. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - Remove unneeded NULL checksJia Jie Ho1-6/+3
NULL check before kfree_sensitive function is not needed. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311301702.LxswfETY-lkp@intel.com/ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - Remove cfb and ofbHerbert Xu2-72/+1
Remove the unused CFB/OFB implementation. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18hwrng: starfive - Fix dev_err_probe return errorJia Jie Ho1-1/+1
Current dev_err_probe will return 0 instead of proper error code if driver failed to get irq number. Fix the return err code. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <error27@gmail.com> Closes: https://lore.kernel.org/r/202311160649.3GhKCfhd-lkp@intel.com/ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - Pad adata with zeroesJia Jie Ho1-2/+4
Aad requires padding with zeroes up to 15 bytes in some cases. This patch increases the allocated buffer size for aad and prevents the driver accessing uninitialized memory region. v1->v2: Specify reason for alloc size change in descriptions. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - RSA poll csr for done statusJia Jie Ho3-45/+22
Hardware could not clear irq status without resetting the entire module. Driver receives irq immediately when mask bit is cleared causing intermittent errors in RSA calculations. Switch to use csr polling for done status instead. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - Update driver dependenciesJia Jie Ho1-1/+1
Change AMBA_PL08X to required dependency as the hash ops depends on it for data transfer. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: jh7110 - Correct deferred probe returnChanho Park1-7/+3
This fixes list_add corruption error when the driver is returned with -EPROBE_DEFER. It is also required to roll back the previous probe sequences in case of deferred_probe. So, this removes 'err_probe_defer" goto label and just use err_dma_init instead. Fixes: 42ef0e944b01 ("crypto: starfive - Add crypto engine support") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18crypto: starfive - remove unnecessary alignmask for ahashesEric Biggers1-11/+2
The crypto API's support for alignmasks for ahash algorithms is nearly useless, as its only effect is to cause the API to align the key and result buffers. The drivers that happen to be specifying an alignmask for ahash rarely actually need it. When they do, it's easily fixable, especially considering that these buffers cannot be used for DMA. In preparation for removing alignmask support from ahash, this patch makes the starfive driver no longer use it. This driver did actually rely on it, but only for storing to the result buffer using int stores in starfive_hash_copy_hash(). This patch makes starfive_hash_copy_hash() use put_unaligned() instead. (It really should use a specific endianness, but that's an existing bug.) Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-18pwm: opencores: Add PWM driver supportWilliam Qiu3-0/+246
Add driver for OpenCores PWM Controller. And add compatibility code which based on StarFive SoC. Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-11-14mmc: starfive: Change tuning implementationWilliam Qiu1-97/+40
Before, we used syscon to achieve tuning, but the actual measurement showed little effect, so the tuning implementation was modified here, and it was realized by reading and writing the UHS_REG_EXT register. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/20230922062834.39212-3-william.qiu@starfivetech.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-11-13clocksource: Add JH7110 timer driverXingyu Wu3-0/+392
Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-11-13clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to ↵Xingyu Wu1-1/+46
1.5GHz CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. But now PLL0 rate is 1GHz and the cpu frequency loads become 333/500/500/1000MHz in fact. So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock and the divider of cpu_core before the setting. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 01:43:47 +0300