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2019-03-01Merge tag 'soc-fsl-next-v5.1-4' of ↵Arnd Bergmann8-5/+88
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.1 take4 DPIO driver - Add support for cache stashing and enable it in dpaa2-eth driver GUTS driver - Make fsl_guts_get_svr() API internal in favor of more generic soc_device_match() * tag 'soc-fsl-next-v5.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: dpaa2-eth: configure the cache stashing amount on a queue soc: fsl: dpio: configure cache stashing destination soc: fsl: dpio: enable frame data cache stashing per software portal soc: fsl: guts: make fsl_guts_get_svr() static Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-03-01Merge tag 'tee-misc-for-v5.1' of ↵Arnd Bergmann3-48/+13
https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers OP-TEE driver - dual license for optee_msg.h and optee_smc.h Generic - add cancellation support to client interface * tag 'tee-misc-for-v5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee: tee: optee: update optee_msg.h and optee_smc.h to dual license tee: add cancellation support to client interface Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-28tee: optee: update optee_msg.h and optee_smc.h to dual licenseJerome Forissier2-48/+4
The files optee_msg.h and optee_smc.h (under drivers/tee/optee) contain information originating from the OP-TEE OS project [1] [2], where the licensing terms are BSD 2-Clause. Therefore, apply a dual license to those files. Link: [1] https://github.com/OP-TEE/optee_os/blob/master/core/include/optee_msg.h Link: [2] https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/include/sm/optee_smc.h Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2019-02-28tee: add cancellation support to client interfaceIgor Opaniuk1-0/+9
Add support of cancellation request to the TEE kernel internal client interface. Can be used by software TPM drivers, that leverage TEE under the hood (for instance TPM2.0 mobile profile), for requesting cancellation of time-consuming operations (RSA key-pair generation etc.). Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2019-02-26dpaa2-eth: configure the cache stashing amount on a queueIoana Ciornei1-1/+6
Configure the amount of 64 bytes of frame, annotation and context data that will be cache stashed for a specific frame queue. Since the frame context is not used, configure that only 64 bytes of frame data and 64 bytes of annotation will be stashed. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-02-26soc: fsl: dpio: configure cache stashing destinationIoana Ciornei5-0/+79
Depending on the SoC version and the CPU id, configure the cache stashing destination for a specific dpio. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-02-26soc: fsl: dpio: enable frame data cache stashing per software portalIoana Ciornei1-2/+2
Enable cache stashing on the frame data dequeued using this software portal. Also, enable dropping a stash request transaction when the target request queue is almost full. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-02-26soc: fsl: guts: make fsl_guts_get_svr() staticHoria Geantă1-2/+1
The export of fsl_guts_get_svr() is a left-over, it's currently used only internally and users needing SoC information should use the generic soc_device infrastructure. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Acked-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-02-20hwrng: make symbol 'optee_rng_id_table' staticWei Yongjun1-1/+1
Fixes the following sparse warning: drivers/char/hw_random/optee-rng.c:265:35: warning: symbol 'optee_rng_id_table' was not declared. Should it be static? Fixes: 5fe8b1cc6a03 ("hwrng: add OP-TEE based rng driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20tee: optee: Fix unsigned comparison with less than zeroYueHaibing1-1/+1
The return from the call to tee_client_invoke_func can be a negative error code however this is being assigned to an unsigned variable 'ret' hence the check is always false. Fix this by making 'ret' an int. Detected by Coccinelle ("Unsigned expression compared with zero: ret < 0") Fixes: c3fa24af9244 ("tee: optee: add TEE bus device enumeration support") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20hwrng: Fix unsigned comparison with less than zeroYueHaibing1-2/+2
The return from the call to tee_client_invoke_func can be a negative error code however this is being assigned to an unsigned variable 'ret' hence the check is always false. Fix this by making 'ret' an int. Detected by Coccinelle ("Unsigned expression compared with zero: ret < 0") Fixes: 5fe8b1cc6a03 ("hwrng: add OP-TEE based rng driver") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20tee: fix possible error pointer ctx dereferencingSumit Garg1-1/+3
Add check for valid ctx pointer and then only dereference ctx to configure supp_nowait flag. Fixes: 42bf4152d8a7 ("tee: add supp_nowait flag in tee_context struct") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20hwrng: optee: Initialize some structs using memset instead of bracesNathan Chancellor1-5/+13
Clang warns: drivers/char/hw_random/optee-rng.c:80:31: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct tee_param param[4] = {0}; ^ {} drivers/char/hw_random/optee-rng.c:177:31: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct tee_param param[4] = {0}; ^ {} drivers/char/hw_random/optee-rng.c:212:48: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct tee_ioctl_open_session_arg sess_arg = {0}; ^ {} 3 warnings generated. One way to fix these warnings is to add additional braces like Clang suggests; however, there has been a bit of push back from some maintainers, who just prefer memset as it is unambiguous, doesn't depend on a particular compiler version, and properly initializes all subobjects [1][2]. Do that here so there are no more warnings. [1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/ [2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/ Fixes: 5fe8b1cc6a03 ("hwrng: add OP-TEE based rng driver") Link: https://github.com/ClangBuiltLinux/linux/issues/369 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20tee: optee: Initialize some structs using memset instead of bracesNathan Chancellor1-3/+8
Clang warns: drivers/tee/optee/device.c:39:31: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct tee_param param[4] = {0}; ^ {} drivers/tee/optee/device.c:92:48: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct tee_ioctl_open_session_arg sess_arg = {0}; ^ {} 2 warnings generated. One way to fix these warnings is to add additional braces like Clang suggests; however, there has been a bit of push back from some maintainers, who just prefer memset as it is unambiguous, doesn't depend on a particular compiler version, and properly initializes all subobjects [1][2]. Do that here so there are no more warnings. [1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/ [2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/ Fixes: c3fa24af9244 ("tee: optee: add TEE bus device enumeration support") Link: https://github.com/ClangBuiltLinux/linux/issues/370 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-20Merge tag 'soc-fsl-next-v5.1-3' of ↵Arnd Bergmann2-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.1 take3 DPIO driver - fixed a use after free problem - fixed a memory leak on error path * tag 'soc-fsl-next-v5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: soc: fsl: dpio: fix memory leak of a struct qbman on error exit path soc: fsl: dpio: Use after free in dpaa2_dpio_remove() Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-19soc: fsl: dpio: fix memory leak of a struct qbman on error exit pathColin Ian King1-0/+1
Currently the error check for a null reg leaks a struct qbman that was allocated earlier. Fix this by kfree'ing p on the error exit path. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
Fixes the following sparse warning: drivers/clk/tegra/clk-tegra124-dfll-fcpu.c:244:18: warning: symbol 'tegra210_cpu_cvb_tables' was not declared. Should it be static? Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-16Merge tag 'qcom-drivers-for-5.1-3' of ↵Arnd Bergmann1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/drivers Qualcomm ARM Based Driver Updates for v5.1 - Part 3 * Fixup types in Qualcomm LLCC patch * tag 'qcom-drivers-for-5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: llcc-slice: Fix typos Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-16soc: qcom: llcc-slice: Fix typosAndy Gross1-2/+2
This patch fixes typos in the llcc-slice driver. Fixes: 72d1cd033154 ("qcom: soc: llcc-slice: Clear the global drv_data pointer on error") Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-15Merge tag 'qcom-drivers-for-5.1-2' of ↵Arnd Bergmann2-33/+74
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/drivers Qualcomm ARM Based Driver Updates for v5.1 - Part 2 * Fixups/Cleanup for Qualcomm LLCC * tag 'qcom-drivers-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: qcom: soc: llcc-slice: Consolidate some code qcom: soc: llcc-slice: Clear the global drv_data pointer on error Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'drivers_soc_for_5.1' of ↵Arnd Bergmann2-20/+3
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers soc: ti: couple of non critical fixes for v5.1 - Fix the Clang warning for enum in Navigator dma - Simplify code in ti_sci with DEFINE_SHOW_ATTRIBUTE macro * tag 'drivers_soc_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: soc: ti: knav_dma: Use proper enum in pktdma_init_chan firmware: ti_sci: Change to use DEFINE_SHOW_ATTRIBUTE macro Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux ↵Arnd Bergmann7-17/+787
into arm/drivers This pull request contains Broadcom ARM/ARM64/MIPS based SoCs changes for 5.1, please pull the following: - Stefan updates the BCM2835 SoC driver with downstream properties and uses that to implement a reboot notifier to tell the VC4 firmware when Linux on the ARM CPU is rebooting - Eric adds a proper power domain driver for the BCM283x SoCs and updates a bunch of drivers to have a better and clearer Device Tree definition to support power domains/breaking up of functionality. This requires converting the existing watchdog driver into a MFD and then breaking up the functionality into separate drivers and finally updating the DTS files to leverage the power domains information. - Wei provides a fix for making a symbol static * tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux: ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware. ARM: bcm283x: Extend the WDT DT node out to cover the whole PM block. (v4) soc: bcm: bcm2835-pm: Make local symbol static soc: bcm: Make PM driver default for BCM2835 soc: bcm: bcm2835-pm: Add support for power domains under a new binding. bcm2835-pm: Move bcm2835-watchdog's DT probe to an MFD. dt-bindings: soc: Add a new binding for the BCM2835 PM node. (v4) firmware: raspberrypi: notify VC4 firmware of a reboot soc: bcm2835: sync firmware properties with downstream Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'qcom-drivers-for-5.1' of ↵Arnd Bergmann11-25/+815
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/drivers Qualcomm ARM Based Driver Updates for v5.1 * Add Qualcomm RPMh power domain driver and related changes * Fix issues with sleep/wake sets and batch API in RPMh * Update MAINTAINERS Qualcomm entry * Fixup RMTFS-mem sysfs and uevents * Fix error handling in GSBI * Add SMD-RPM compatible entry for SDM660 * tag 'qcom-drivers-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: smd-rpm: Add sdm660 compatible soc: qcom: gsbi: Fix error handling in gsbi_probe() soc: qcom: rpmh: Avoid accessing freed memory from batch API drivers: qcom: rpmh: avoid sending sleep/wake sets immediately soc: qcom: rmtfs-mem: Make sysfs attributes world-readable soc: qcom: rmtfs-mem: Add class to enable uevents soc: qcom: update config dependencies for QCOM_RPMPD soc: qcom: rpmpd: Drop family A RPM dependency MAINTAINERS: update list of qcom drivers soc: qcom: rpmhpd: Mark mx as a parent for cx soc: qcom: rpmhpd: Add RPMh power domain driver soc: qcom: rpmpd: Add support for get/set performance state soc: qcom: rpmpd: Add a Power domain driver to model corners dt-bindings: power: Add qcom rpm power domain driver bindings OPP: Add support for parsing the 'opp-level' property dt-bindings: opp: Introduce opp-level bindings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tee-bus-for-5.1' of ↵Arnd Bergmann9-5/+549
https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers Introduce TEE bus driver framework - supp_nowait flag for non-blocking tee requests - The tee bus driver framework - OP-TEE TEE bus device enumeration support - An OP-TEE based rng driver * tag 'tee-bus-for-5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee: hwrng: add OP-TEE based rng driver tee: optee: add TEE bus device enumeration support tee: add bus driver framework for TEE based devices tee: add supp_nowait flag in tee_context struct
2019-02-15Merge tag 'hisi-drivers-for-5.1' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann1-3/+2
into arm/drivers ARM64: hisi: SoC driver updates for 5.1 - Add compatibility support for different FWs in the hisi LPC bus driver * tag 'hisi-drivers-for-5.1' of git://github.com/hisilicon/linux-hisi: bus: hisi_lpc: Don't fail probe for unrecognised child devices Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tegra-for-5.1-clk' of ↵Arnd Bergmann7-98/+913
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers clk: tegra: Changes for v5.1-rc1 This contains a couple of prerequisite patches to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 clk: tegra: dfll: add CVB tables for Tegra210 clk: tegra: dfll: round down voltages based on alignment clk: tegra: dfll: support PWM regulator control clk: tegra: dfll: CVB calculation alignment with the regulator clk: tegra: dfll: registration for multiple SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tegra-for-5.1-cpufreq' of ↵Arnd Bergmann3-42/+7
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers cpufreq: tegra: Add support for Tegra210 This uses the DFLL clock support to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: cpufreq: dt-platdev: add Tegra210 to blacklist cpufreq: tegra124: extend to support Tegra210 cpufreq: tegra124: do not handle the CPU rail Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tegra-for-5.1-soc' of ↵Arnd Bergmann3-140/+298
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.1-rc1 This contains a couple of miscellaneous fixes for minor issues and a largish rework of the PMC driver to make it work on systems where the PMC has been locked down and can only be accessed from secure firmware. * tag 'tegra-for-5.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Support systems where PMC is marked secure soc/tegra: pmc: Explicitly initialize all fields soc/tegra: pmc: Make alignment consistent soc/tegra: pmc: Pass struct tegra_pmc * where possible soc/tegra: pmc: Make tegra_powergate_is_powered() a local function soc/tegra: pmc: Add missing kerneldoc soc/tegra: pmc: Sort includes alphabetically soc/tegra: pmc: Use TEGRA186_ prefix for GPIO names soc/tegra: fuse: Fix typo in tegra210_init_speedo_data soc/tegra: fuse: Fix illegal free of IO base address Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tegra-for-5.1-firmware' of ↵Arnd Bergmann5-226/+735
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers firmware: tegra: Changes for v5.1-rc1 These changes add support for BPMP on Tegra210. * tag 'tegra-for-5.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: firmware/tegra: Enable Tegra186 BPMP support on Tegra194 firmware: tegra: Conditionally support SoC generations firmware: tegra: bpmp-tegra186: Remove unused includes firmware: tegra: add bpmp driver for Tegra210 firmware: tegra: Refactor BPMP driver firmware: tegra: Reword messaging terminology Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into ↵Arnd Bergmann6-17/+303
arm/drivers Reset controller changes for v5.1 This adds the include/linux/reset directory to MAINTAINERS for reset specific headers and adds headers for sunxi and socfpga in there to get rid of a few extern function declarations. There is a new reset driver for the Broadcom STB reset controller and the i.MX7 system reset controller driver is extended to support i.MX8MQ as well. Finally, there is a new header with reset id constants for the Meson G12A SoC, which has a reset controller identical to Meson AXG and thus can reuse its driver and DT bindings. * tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: meson: add g12a bindings reset: imx7: Add support for i.MX8MQ IP block variant reset: imx7: Add plubming to support multiple IP variants reset: Add Broadcom STB SW_INIT reset controller driver dt-bindings: reset: Add document for Broadcom STB reset controller reset: socfpga: declare socfpga_reset_init in a header file reset: sunxi: declare sun6i_reset_init in a header file MAINTAINERS: use include/linux/reset for reset controller related headers dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'amlogic-drivers' of ↵Arnd Bergmann2-2/+212
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers Amlogic: driver updates for v5.1 - clock measure: add support for G12a SoC family - misc. fixes * tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: soc: amlogic: clk-measure: add axg and g12a support dt-bindings: amlogic: add new compatible devices to clk_measure soc: amlogic: canvas: Fix meson_canvas_get when probe failed soc: amlogic: add missing of_node_put() Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'imx-drivers-5.1' of ↵Arnd Bergmann5-16/+171
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.1: - Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is going to be used on more SoCs than just i.MX8MQ. - Add power domain information into SCU bindings document. - Add support of start/stop a CPU into imx firmware driver. - Support multiple address ranges per child node for imx-weim bus driver. * tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: firmware: imx: Add support to start/stop a CPU soc: imx: Break dependency on SOC_IMX8MQ for GPCv2 firmware: imx: scu-pd: add fallback compatible string support dt-bindings: fsl: scu: add imx8qm scu power domain support dt-bindings: fsl: scu: add fallback compatible string for power domain bus: imx-weim: guard against timing configuration conflicts bus: imx-weim: support multiple address ranges per child node dt-bindings: bus: imx-weim: document multiple address ranges per child node soc: imx: gpcv2: handle reset clocks soc: imx: gpcv2: handle additional power-down bits in handshake register Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann11-0/+901
arm/drivers arm64: zynqmp: SoC changes for v5.1 - Extend firmware interface with reset, nvmem, power management and power domain support - Add reset, nvmem driver, power management and power domain drivers - * tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx: drivers: soc: xilinx: Add ZynqMP power domain driver firmware: xilinx: Add APIs to control node status/power dt-bindings: power: Add ZynqMP power domain bindings drivers: soc: xilinx: Add ZynqMP PM driver firmware: xilinx: Implement ZynqMP power management APIs dt-bindings: soc: Add ZynqMP PM bindings nvmem: zynqmp: Added zynqmp nvmem firmware driver dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver firmware: xilinx: Add zynqmp_pm_get_chipid() API reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller. dt-bindings: reset: Add bindings for ZynqMP reset driver firmware: xilinx: Add reset API's Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-13qcom: soc: llcc-slice: Consolidate some codeJordan Crouse1-22/+20
Make the code a little bit clearer (and use less gotos) by consolidating some of the initialization. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-13qcom: soc: llcc-slice: Clear the global drv_data pointer on errorJordan Crouse2-17/+60
Currently the data structure for llc-slice is devm allocated and stored as a global but never cleared if the probe function fails. This is a problem because devm managed memory gets freed on probe failure the API functions could access the pointer after it has been freed. Initialize the drv_data pointer to an error and reset it to an error on probe failure or device destroy and add protection to the API functions to make sure the memory doesn't get accessed. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-12drivers: soc: xilinx: Add ZynqMP power domain driverJolly Shah5-0/+347
The zynqmp-genpd driver communicates the usage requirements for logical power domains / devices to the platform FW. FW is responsible for choosing appropriate power states, taking Linux' usage information into account. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-12firmware: xilinx: Add APIs to control node status/powerRajan Vaja1-0/+58
Add Xilinx ZynqMP firmware APIs to control node status and power. These APIs allows turning on/off power domain and setting capabilities of devices present in power domain. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-12drivers: soc: xilinx: Add ZynqMP PM driverRajan Vaja3-0/+190
Add ZynqMP PM driver. PM driver provides power management support for ZynqMP. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-12firmware: xilinx: Implement ZynqMP power management APIsJolly Shah1-0/+29
Add Xilinx ZynqMP firmware APIs to set suspend mode and inform firmware that master has initialized its own power management. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-11firmware: imx: Add support to start/stop a CPUDaniel Baluta1-0/+38
This is done via RPC call to SCU. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-08bus: hisi_lpc: Don't fail probe for unrecognised child devicesJohn Garry1-3/+2
Currently for ACPI-based FW we fail the probe for an unrecognised child HID. However, there is FW in the field with LPC child devices having fake HIDs, namely "IPI0002", which was an IPMI device invented to support the initial out-of-tree LPC host driver, different from the final mainline version. To provide compatibility support for these dodgy FWs, just discard the unrecognised HIDs instead of failing the probe altogether. Tested-by: Zengruan Ye <yezengruan@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-02-08soc: amlogic: clk-measure: add axg and g12a supportJerome Brunet1-0/+196
Add support for the axg and g12a SoC family in amlogic clk measure Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: squashed some fixups from Martin] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-08soc: amlogic: canvas: Fix meson_canvas_get when probe failedNeil Armstrong1-1/+12
When probe fails, a platforn_device is still associated to the node, but dev_get_drvdata() returns NULL. Handle this case by returning a consistent error. Fixes: d4983983d987 ("soc: amlogic: add meson-canvas driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com> [khilman: fixed minor typo in comment ] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-07firmware/tegra: Enable Tegra186 BPMP support on Tegra194Thierry Reding3-3/+7
The BPMP implementation on Tegra194 is mostly compatible with the implementation on Tegra186, so make sure the latter is available when support for Tegra194 is enabled. Suggested-by: Timo Alho <talho@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07firmware: tegra: Conditionally support SoC generationsThierry Reding2-0/+12
Only include support for Tegra210 and Tegra186 in the BPMP driver if support for those SoCs was selected. This fixes a build failure seen on 32-bit ARM allmodconfig builds, but could also happen on 64-bit ARM builds if either Tegra210 or Tegra186 were not selected. Reported-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07soc: amlogic: add missing of_node_put()wen yang1-1/+4
The call to of_parse_phandle returns a node pointer with refcount incremented thus it must be explicitly decremented here after the last usage. Signed-off-by: Wen Yang <yellowriver2010@hotmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: d4983983d987 ("soc: amlogic: add meson-canvas driver") Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-06cpufreq: dt-platdev: add Tegra210 to blacklistJoseph Lo1-0/+1
Tegra210 uses "tegra124-cpufreq" platform driver to register device data for "cpufreq-dt" driver. So add it in the blacklist for "cpufreq-dt-platdev" driver to drop that. Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06cpufreq: tegra124: extend to support Tegra210Joseph Lo1-1/+2
Tegra210 uses the same methodology as Tegra124 for CPUFreq controlling that based on DFLL clock. So extending this driver to support Tegra210. Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06cpufreq: tegra124: do not handle the CPU railJoseph Lo2-41/+4
The Tegra124 cpufreq driver has no information to handle the Vdd-CPU rail. So this driver shouldn't handle for the CPU clock switching from DFLL to other PLL clocks. It was designed to work on DFLL clock only, which handle the frequency/voltage scaling in the background. This patch removes the driver dependency of the CPU rail, as well as not allow it to be built as a module and remove the removal function. So it can keep working on DFLL clock. Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
Tegra210 has a DFLL as well and can share the majority of the code with the Tegra124 implementation. So build the same code for both platforms. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-21 03:11:12 +0300