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2024-01-12clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to ↵Xingyu Wu1-1/+48
1.5GHz CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. But now PLL0 rate is 1GHz and the cpu frequency loads become 333/500/500/1000MHz in fact. So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock and the divider of cpu_core before the setting. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11net: phy: motorcomm: Add pad drive strength cfg supportshanlong.li1-24/+38
The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data, and the default strength may not be suitable for all boards. So add configurable options to better match the boards.(e.g. StarFive VisionFive 2) Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2024-01-11net: phy: motorcomm: Add pad drive strength cfg supportSamin Guo1-0/+32
The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data, and the default strength may not be suitable for all boards. So add configurable options to better match the boards.(e.g. StarFive VisionFive 2) Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2024-01-11net: phy: motorcomm: uninitialized variables in yt8531_link_change_notify()Dan Carpenter1-3/+3
These booleans are never set to false, but are just used without being initialized. Fixes: 4ac94f728a58 ("net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy") Signed-off-by: Dan Carpenter <error27@gmail.com> Reviewed-by: Frank Sae <Frank.Sae@motor-comm.com> Link: https://lore.kernel.org/r/Y+xd2yJet2ImHLoQ@kili Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-11net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phyFrank Sae2-3/+207
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have verified the driver on AM335x platform with yt8531 board. On the board, yt8531 gigabit ethernet phy works in utp mode, RGMII interface, supports 1000M/100M/10M speeds, and wol(magic package). Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: Add dts support for Motorcomm yt8531s gigabit ethernet phyFrank Sae1-24/+27
Add dts support for Motorcomm yt8531s gigabit ethernet phy. Change yt8521_probe to support clk config of yt8531s. Becase yt8521_probe does the things which yt8531s is needed, so removed yt8531s function. This patch has been verified on AM335x platform with yt8531s board. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: Add dts support for Motorcomm yt8521 gigabit ethernet phyFrank Sae1-54/+199
Add dts support for Motorcomm yt8521 gigabit ethernet phy. Add ytphy_rgmii_clk_delay_config function to support dst config for the delay of rgmii clk. This funciont is common for yt8521, yt8531s and yt8531. This patch has been verified on AM335x platform. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phyFrank Sae1-4/+51
Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy. This is a preparatory patch. Add BIT macro for 0xA012 reg, and supplement for 0xA001 and 0xA003 reg. These will be used to support dts. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: motorcomm: change the phy id of yt8521 and yt8531s to lowercaseFrank Sae1-2/+2
The phy id is usually defined in lower case. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230128063558.5850-2-Frank.Sae@motor-comm.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-11net: phy: fix the spelling problem of SentinelFrank Sae1-1/+1
CHECK: 'sentinal' may be misspelled - perhaps 'sentinel'? Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230128063558.5850-1-Frank.Sae@motor-comm.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-11net: phy: add Motorcomm YT8531S phy id.Frank2-6/+48
We added patch for motorcomm.c to support YT8531S. This patch has been tested on AM335x platform which has one YT8531S interface card and passed all test cases. The tested cases indluding: YT8531S UTP function with support of 10M/100M/1000M; YT8531S Fiber function with support of 100M/1000M; and YT8531S Combo function that supports auto detection of media type. Since most functions of YT8531S are similar to YT8521 and we reuse some codes for YT8521 in the patch file. Signed-off-by: Frank <Frank.Sae@motor-comm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: fix yt8521 duplicated argument to & or |Frank1-4/+4
cocci warnings: (new ones prefixed by >>) >> drivers/net/phy/motorcomm.c:1122:8-35: duplicated argument to & or | drivers/net/phy/motorcomm.c:1126:8-35: duplicated argument to & or | drivers/net/phy/motorcomm.c:1130:8-34: duplicated argument to & or | drivers/net/phy/motorcomm.c:1134:8-34: duplicated argument to & or | The second YT8521_RC1R_GE_TX_DELAY_xx should be YT8521_RC1R_FE_TX_DELAY_xx. Fixes: 70479a40954c ("net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phy") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Frank <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phyFrank2-3/+1634
Add a driver for the motorcomm yt8521 gigabit ethernet phy. We have verified the driver on StarFive VisionFive development board, which is developed by Shanghai StarFive Technology Co., Ltd.. On the board, yt8521 gigabit ethernet phy works in utp mode, RGMII interface, supports 1000M/100M/10M speeds, and wol(magic package). Signed-off-by: Frank <Frank.Sae@motor-comm.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-11drivers: include cpufreq/Kconfig for riscvZoltan HERPAI1-0/+2
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
2024-01-11driver: regulator: axp20x: Support AXP15060 variant.ziv.xu1-8/+283
Add axp15060 variant support to axp20x Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2024-01-11driver: mfd: axp20x: Add support for AXP15060ziv.xu2-30/+345
axp20x add support for AXP15060 Signed-off-by: ziv.xu <ziv.xu@starfive.com>
2024-01-11dmaengine: dw-axi-dmac: Increase polling time to DMA transmission completion ↵Walker Chen1-1/+1
status The bit DMAC_CHEN[0] is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. This time requires at least 40 milliseconds on JH7110 SoC, otherwise an error message 'failed to stop' will be reported. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2024-01-11dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMAWalker Chen2-5/+34
Add DMA reset operation in device probe and use different configuration on CH_CFG registers according to match data. Update all uses of of_device_is_compatible with of_device_get_match_data. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2024-01-11hwmon: (sfctemp) Add StarFive JH71x0 temperature sensorEmil Renner Berthing3-0/+342
Add driver for the StarFive JH71x0 temperature sensor. You can enable/disable it and read temperature in milli Celcius through sysfs. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-01-11mmc: starfive: Add sdio/emmc driver supportWilliam Qiu3-0/+197
Add sdio/emmc driver support for StarFive JH7110 soc. Tested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2024-01-11drivers: watchdog: Add StarFive Watchdog driverXingyu Wu3-0/+620
Add watchdog driver for the StarFive JH7100 and JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
2024-01-11hwrng: starfive - Enable compile testingHerbert Xu1-2/+1
Enable compile testing for jh7110. Also remove the dependency on HW_RANDOM. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-11hwrng: starfive - Add TRNG driver for StarFive SoCJia Jie Ho3-0/+405
This adds driver support for the hardware random number generator in Starfive SoCs and adds StarFive TRNG entry to MAINTAINERS. Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2024-01-11cpufreq: dt-platdev: Add JH7110 SOC to the allowlistMason Huo1-0/+2
Add the compatible strings for supporting the generic cpufreq driver on the StarFive JH7110 SoC. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2024-01-11pcie: starfive: add StarFive JH7110 PCIe driver.Minda Chen3-0/+967
Add PCIe controller driver for StarFive JH7110 SoC platform. The PCIe controller is PCIe 2.0, single lane. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-01-11spi: cadence-quadspi: Add support for StarFive JH7110 QSPIWilliam Qiu2-2/+21
Add QSPI reset operation in device probe and add RISCV support to QUAD SPI Kconfig. Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2024-01-11usb: cdns3: Add StarFive JH7110 USB driverMinda Chen3-0/+258
Adds Specific Glue layer to support USB peripherals on StarFive JH7110 SoC. There is a Cadence USB3 core for JH7110 SoCs, the cdns core is the child of this USB wrapper module device. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Peter Chen <peter.chen@kernel.org>
2024-01-11phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen3-0/+215
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-01-11phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen3-0/+162
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-01-11media: starfive: Add VIN driverJack Zhu6-2/+1598
Add Video In Controller driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11media: starfive: Add ISP driverJack Zhu6-2/+1551
Add ISP driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11media: starfive: Add video driverJack Zhu3-1/+961
Add video driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11media: starfive: Add basic driverJack Zhu7-0/+573
Add basic platform driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2024-01-11media: cadence: Add support for JH7110 SoCJack Zhu1-0/+1
Add support for Starfive JH7110 SoC which has the cadence csi2 receiver. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11media: cadence: Add support for external dphyJack Zhu1-10/+56
Add support for external MIPI D-PHY. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11media: cadence: Add operation on resetJack Zhu1-5/+35
Add operation on reset for Cadence MIPI-CSI2 RX Controller. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2024-01-11phy: starfive: Add mipi dphy rx supportChanghuang Liang5-0/+318
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2024-01-11soc: starfive: Add JH7110 AON PMU supportChanghuang Liang1-5/+52
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the dphy rx/tx power switch. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2024-01-11soc: starfive: Extract JH7110 pmu private operationsChanghuang Liang1-27/+62
Move JH7110 private operation into private data of compatible. Convenient to add AON PMU which would not have interrupts property. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
2024-01-11soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEChanghuang Liang1-2/+2
Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2024-01-11crypto: starfive - Fix driver dependenciesJia Jie Ho1-2/+1
Kconfig updated to depend on DMADEVICES instead of selecting it. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202305191929.Eq4OVZ6D-lkp@intel.com/ Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-11crypto: starfive - Add crypto engine supportJia Jie Ho6-0/+287
Adding device probe and DMA init for StarFive cryptographic module. Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-01-11pwm: starfive: Add PWM driver supportWilliam Qiu3-0/+256
Add Pulse Width Modulation driver support for StarFive JH7110 soc. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2024-01-11clocksource: Add StarFive timer driverXingyu Wu4-0/+499
Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11clk: starfive: update jh7110 PLL clock drivershanlong.li2-306/+227
Update the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2024-01-11reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets supportXingyu Wu1-0/+30
Add new struct members and auxiliary_device_id of resets to support System-Top-Group, Image-Signal-Process and Video-Output on the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11clk: starfive: Add StarFive JH7110 Video-Output clock driverXingyu Wu3-0/+251
Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driverXingyu Wu4-0/+250
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2024-01-11clk: starfive: Add StarFive JH7110 System-Top-Group clock driverEmil Renner Berthing3-0/+185
Add driver for the StarFive JH7110 System-Top-Group clock controller. Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
2024-01-11net: stmmac: dwmac-starfive: Add phy interface settingsSamin Guo1-0/+48
dwmac supports multiple modess. When working under rmii and rgmii, you need to set different phy interfaces. According to the dwmac document, when working in rmii, it needs to be set to 0x4, and rgmii needs to be set to 0x1. The phy interface needs to be set in syscon, the format is as follows: starfive,syscon: <&syscon, offset, shift> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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