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path: root/drivers/usb/dwc2/hw.h
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2018-10-02usb: dwc2: Add definitions for new registersGrigor Tovmasyan1-0/+13
New registers were added to dwc otg core. GREFCLK - This register used to control ref_clk parameters. GINTSTS2 - New WKUP_ALERT interrupt was added. GINTMSK2 - Mask register for GINTSTS2. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-10-02usb: dwc2: Update registers definitions to support service intervalGrigor Tovmasyan1-0/+2
Added GHWCFG4_SERVICE_INTERVAL_SUPPORTED and DCTL_SERVICE_INTERVAL_SUPPORTED bits definitions to support service interval based scheduling. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-05-15usb: dwc2: Add Interpacket Gap(IPG) feature supportGrigor Tovmasyan1-0/+2
Added GHWCFG4_IPG_ISOC_SUPPORTED and DCFG_IPG_ISOC_SUPPORDED bits definitions to enable/disable IPG feature. Added ipg_isoc_en core parameter which will indicate IPG support enable/disable and initialize it. Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-13usb: dwc2: Rename GLPMCFG... definitionsSevak Arakelyan1-18/+20
Make field names of GLPMCFG register in definitions to be the same with the databook. Signed-off-by: Sevak Arakelyan <sevaka@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-13usb: dwc2: Add ACG support to the driverRazmik Karapetyan1-0/+5
Added function for supporting Active Clock Gating functionality in the driver. PCGCCTL1 (Power and Clock Control) register will be used for controlling the core`s active clock gating feature, and the previously reserved 12th bit in GHWCFG4 now indicates that the controller supports the Dynamic Power Reduction (Active Clock Gating) during no traffic scenarios such as L0, idle, resume and suspend states. dwc2_enable_acg() function sets GATEEN bit in PCGCCTL1 register and enables ACG, if it supported. According to ACG functional specification, enabling of ACG feature in host mode done in host initialization, before turning Vbus on, specifically in dwc2_core_host_init function. Enabling of ACG feature in device mode done in device initialization, before clearing the SftDiscon bit in DCTL. This bit was cleared in dwc2_hsotg_core_connect() function.So dwc2_enable_acg() called before dwc2_core_connect() calls. Signed-off-by: Razmik Karapetyan <razmik@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-03-13usb: dwc2: Remove version check in GSNPSIDGevorg Sahakyan1-0/+1
Only check the ID portion of the GSNPSID register and don’t check the version. This will allow the driver to work with version 4.00a and later of the DWC_hsotg IP. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-11-04USB: add SPDX identifiers to all remaining files in drivers/usb/Greg Kroah-Hartman1-0/+1
It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/usb/ and include/linux/usb* files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com> Acked-by: Johan Hovold <johan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-11usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode ↵Bruno Herrera1-0/+2
(internal PHY) This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver. Also add the dwc2_set_params function for stm32f4 otg fs. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Bruno Herrera <bruherrera@gmail.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2017-01-24usb: dwc2: Cleanup some checkpatch issuesJohn Youn1-298/+298
This commmit is the result of running checkpatch --fix. The results were verified for correctness. Some of the fixes result in line over 80 char which we will fix manually later. The following is a summary of what was done by checkpatch: * Remove externs on function prototypes. * Replace symbolic permissions with octal. * Align code to open parens. * Replace 'unsigned' with 'unsigned int'. * Remove unneccessary blank lines. * Add blank lines after declarations. * Add spaces around operators. * Remove unnecessary spaces after casts. * Replace 'x == NULL' with '!x'. * Replace kzalloc() with kcalloc(). * Concatenate multi-line strings. * Use the BIT() macro. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: gadget: Enable the BNA interruptVahram Aharonyan1-0/+1
Enable the BNA (Buffer Not Available) interrupt in descriptor DMA mode. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: gadget: Enable descriptor DMA modeVahram Aharonyan1-0/+1
Add DCFG register field macro for descriptor DMA mode and update core initialization routine to set that bit accordingly. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: host: Rename MAX_DMA_DESC_SIZE to HOST_DMA_NBYTES_LIMITVahram Aharonyan1-1/+1
Rename MAX_DMA_DESC_SIZE to HOST_DMA_NBYTES_LIMIT as it stores value of host DMA descriptor transfer bytes' limit. Values are different in case of gadget DMA descriptors. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: gadget: Add DMA descriptor status quadlet fieldsVahram Aharonyan1-0/+37
Add device mode DMA transfer descriptor status quadlet field notations. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: Make the DMA descriptor structure packedVahram Aharonyan1-1/+1
Make the DMA descriptor structure packed to guarantee alignment and size in memory. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-11-18usb: dwc2: Update DMA descriptor structureVahram Aharonyan1-2/+3
Rename DMA descriptor structure from dwc2_hcd_dma_desc to dwc2_dma_desc as it is applies to both host and gadget. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-09-08usb: dwc2: Add delay to core soft resetJohn Youn1-0/+1
Add a delay to the core soft reset function to account for the IDDIG debounce filter. If the current mode is host, either due to the force mode bit being set (which persists after core reset) or the connector id pin, a core soft reset will temporarily reset the mode to device and a delay from the IDDIG debounce filter will occur before going back to host mode. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-06-21usb: dwc2: gadget: Final fixes for BDMA ISOCVardan Mikayelyan1-0/+1
Done fixes and tested hsotg gadget's BDMA mode. Tested Control, Bulk, Isoc, Inter transfers. Added code for isoc transfers, removed unusable code, done minor fixes. Affected functions and IRQ handlers: - dwc2_hsotg_start_req(), - dwc2_hsotg_ep_enable(), - dwc2_hsotg_ep_queue(), - dwc2_hsotg_handle_outdone(), - GINTSTS_GOUTNAKEFF handler, Removed 'has_correct_parity' flag from 'dwc2_hsotg_ep' struct. Before this patch series, to set the data pid the DWC2 gadget driver was toggling the even/odd until it match, then were leaving it set. But now I have added mechanism to set pid and excluded all code where this flag was set. Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2016-06-21usb: dwc2: Add missing register field definitionsVardan Mikayelyan1-0/+13
Added register field definitions, register names are according DWC-OTG databook. Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2015-12-15usb: dwc2: host: fix descriptor list address maskingMian Yousaf Kaukab1-4/+0
Masks for HCDMA.CTD and HCDMA.DMAAddr are incorrect. As we always start from first descriptor, no need to mask the address anyway. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-10-02usb: dwc2: gadget: parity fix in isochronous modeRoman Bacik1-0/+1
USB OTG driver in isochronous mode has to set the parity of the receiving microframe. The parity is set to even by default. This causes problems for an audio gadget, if the host starts transmitting on odd microframes. This fix uses Incomplete Periodic Transfer interrupt to toggle between even and odd parity until the Transfer Complete interrupt is received. Signed-off-by: Roman Bacik <rbacik@broadcom.com> Reviewed-by: Abhinav Ratna <aratna@broadcom.com> Reviewed-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-30usb: dwc2: gadget: replace constants with definesMian Yousaf Kaukab1-0/+1
Defines are more readable and searchable than constants. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13usb: dwc2: gadget: don't process XferCompl on setup packetMian Yousaf Kaukab1-0/+1
Only process DOEPINT.XferCompl on data packet as DOEPINTn.SetUp can occur with or without DOEPINT.XferCompl. When DOEPINT.SetUp occurs with DOEPINT.XferCompl, only DOEPINT.SetUp needs to be handled. Moreover, ignore DOEPINT.XferCompl when it occurs with DOEPINT.StupPktRcvd as driver needs to wait for DOEPINT.SetUp to continue. Tested-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-04-25usb: dwc2: add defines to support s3c-hsotg driverDinh Nguyen1-5/+7
In preparation of combining the dwc2/s3c-hsotg driver in a single DRD driver, the defines in dwc2/hw.h needs to get updated so that the s3c-hsotg driver can use them. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> [ jh,rb - For gadget part only: ] Tested-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> [ pz - Tested host part only. ] Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-14Move DWC2 driver out of stagingPaul Zimmerman1-0/+809
The DWC2 driver should now be in good enough shape to move out of staging. I have stress tested it overnight on RPI running mass storage and Ethernet transfers in parallel, and for several days on our proprietary PCI-based platform. Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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