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2022-02-28Merge tag 'ti-driver-soc-for-v5.18' of ↵Arnd Bergmann4-17/+16
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers TI Driver updates for v5.18 * Fixups for k3-ringacc, smartreflex, tisci, wkup_m3_ipc * Device detection for am62x. * tag 'ti-driver-soc-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: k3-socinfo: Add AM62x JTAG ID soc: ti: wkup_m3_ipc: Fix IRQ check in wkup_m3_ipc_probe firmware: ti_sci: inproper error handling of ti_sci_probe firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined soc: ti: smartreflex: Use platform_get_irq_optional() to get the interrupt soc: ti: k3-ringacc: Use devm_bitmap_zalloc() when applicable Link: https://lore.kernel.org/r/20220228120655.wobd72acngl2bz6k@ecard Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-28Merge tag 'tegra-for-5.18-soc' of ↵Arnd Bergmann2-8/+32
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.18-rc1 This contains the final bit to enable advanced power management on Tegra20 and Tegra30. It also contains some cleanups and wake event support on Tegra234. * tag 'tegra-for-5.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: bpmp: cleanup double word in comment soc/tegra: pmc: Add Tegra234 wake events soc/tegra: fuse: Explicitly cast to/from __iomem soc/tegra: fuse: Update nvmem cell list soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Link: https://lore.kernel.org/r/20220225164741.1064416-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-28soc: ti: k3-socinfo: Add AM62x JTAG IDVignesh Raghavendra1-0/+1
Add JTAG ID entry to help identify AM62x SoC in kernel. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220225120239.1303821-2-vigneshr@ti.com
2022-02-28soc: mediatek: add MTK mutex support for MT8186Yongqiang Niu1-0/+45
Add MTK mutex support for MT8186 SoC. We need MTK mutex to control timing of display modules and there are two display pipelines for MT8186 including internal and external display. MTK mutex for internal display: - Timing source: DSI - Control modules: OVL0/RDMA0/COLOR0/CCORR/AAL0/GAMMA/POSTMASK0/DITHER MTK mutex for external display: - Timing source : DPI - Control modules: OVL_2L0/RDMA1 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: mmsys: add mt8186 mmsys routing tableYongqiang Niu2-0/+124
Add new routing table for MT8186. In MT8186, there are two routing pipelines for internal and external display. Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0-> DITHER->DSI0 External display: OVL_2L0->RDMA1->DPI0 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: pm-domains: Add support for mt8186Chun-Jie Chen2-0/+349
Add power domain control data in mt8186. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: pm-domains: Add support for mt8195Chun-Jie Chen3-1/+619
Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: pm-domains: Move power status offset to power domain dataChun-Jie Chen6-12/+110
MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-5-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: pm-domains: Remove unused macroChun-Jie Chen1-2/+0
Due to clk resource data will be allocated dynamically by searching parent count of clk in power domain node, so remove the unused marco MAX_SUBSYS_CLKS for static allocation. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-4-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: pm-domains: Add wakeup capacity support in power domainChun-Jie Chen1-0/+3
Due to some power domain needs to keep on for wakeup in system suspend, so add GENPD_FLAG_ACTIVE_WAKEUP support in Mediatek power domain driver. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-3-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-25Merge tag 'imx-drivers-5.18' of ↵Arnd Bergmann2-3/+66
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.18: - Drop LS1021A device check from soc-imx driver as it's unneeded since commit commit 4ebd29f91629 ("soc: imx: Register SoC device only on i.MX boards"). - Add support for power domains provided by the VPU blk-ctrl on the i.MX8MQ. - Add resource owner management API which will be used to check whether M4 is under control of Linux. - Add VPU MU resources support into SCU power domain driver. - Support DT overlay for WEIM bus driver with OF reconfiguration notifier handler. * tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: bus: imx-weim: add DT overlay support for WEIM bus firmware: imx: scu-pd: imx8q: add vpu mu resources firmware: imx: add get resource owner api soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains soc: imx: Remove Layerscape check Link: https://lore.kernel.org/r/20220222075226.160187-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'soc-fsl-fix-v5.17' of ↵Arnd Bergmann3-7/+13
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/fixes NXP/FSL SoC driver fixes for v5.17 - Add missing SoC compatible in existing binding - Replace kernel.h with the necessary inclusions - MAINTAINERS file fixes - Fix memory allocation failure check in guts driver - Various cleanups and minor fixes * tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: soc: fsl: qe: Check of ioremap return value soc: fsl: qe: fix typo in a comment soc: fsl: guts: Add a missing memory allocation failure check soc: fsl: guts: Revert commit 3c0d64e867ed soc: fsl: Correct MAINTAINERS database (SOC) soc: fsl: Correct MAINTAINERS database (QUICC ENGINE LIBRARY) soc: fsl: Replace kernel.h with the necessary inclusions dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a dt-bindings: qoriq-clock: add missing compatible for lx2160a Link: https://lore.kernel.org/r/20220219012208.21835-1-leoyang.li@nxp.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'at91-soc-5.18' of ↵Arnd Bergmann5-0/+207
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 & POLARFIRE SoC #1 for 5.18: - sama7g5: CPU idle support with CPUFreq operating points defined in DT - polarfire: addition of the soc system controller * tag 'at91-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: soc: add microchip polarfire soc system controller ARM: at91: Kconfig: select PM_OPP ARM: at91: PM: add cpu idle support for sama7g5 ARM: at91: ddr: fix typo to align with datasheet naming ARM: at91: ddr: align macro definitions ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency Link: https://lore.kernel.org/r/20220225121943.71494-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25soc/tegra: pmc: Add Tegra234 wake eventskartik1-3/+9
Enable the Tegra RTC alarm and power key wake-ups for Tegra234 Signed-off-by: kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25soc: add microchip polarfire soc system controllerConor Dooley5-0/+207
This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220217101349.2374873-2-conor.dooley@microchip.com
2022-02-25Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-11/+4
tools/testing/selftests/net/mptcp/mptcp_join.sh 34aa6e3bccd8 ("selftests: mptcp: add ip mptcp wrappers") 857898eb4b28 ("selftests: mptcp: add missing join check") 6ef84b1517e0 ("selftests: mptcp: more robust signal race test") https://lore.kernel.org/all/20220221131842.468893-1-broonie@kernel.org/ drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c fb7e76ea3f3b6 ("net/mlx5e: TC, Skip redundant ct clear actions") c63741b426e11 ("net/mlx5e: Fix MPLSoUDP encap to use MPLS action information") 09bf97923224f ("net/mlx5e: TC, Move pedit_headers_action to parse_attr") 84ba8062e383 ("net/mlx5e: Test CT and SAMPLE on flow attr") efe6f961cd2e ("net/mlx5e: CT, Don't set flow flag CT for ct clear flow") 3b49a7edec1d ("net/mlx5e: TC, Reject rules with multiple CT actions") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-02-24soc: qcom: rpmpd: Add MSM8226 supportLuca Weiss1-0/+17
Add the power domains preset in MSM8226. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220220223004.507739-2-luca@z3ntu.xyz
2022-02-24Merge tag 'dtpm-v5.18' of https://git.linaro.org/people/daniel.lezcano/linuxRafael J. Wysocki3-0/+74
Pull DTPM (Dynamic Thermal Power Management) changes for 5.18-rc1 from Daniel Lezcano: "- Added dtpm hierarchy description (Daniel Lezcano) - Changed the locking scheme (Daniel Lezcano) - Fixed dtpm_cpu cleanup at exit time and missing virtual dtpm pointer release (Daniel Lezcano)" * tag 'dtpm-v5.18' of https://git.linaro.org/people/daniel.lezcano/linux: dtpm/soc/rk3399: Add the ability to unload the module powercap/dtpm_cpu: Add exit function powercap/dtpm: Move the 'root' reset place powercap/dtpm: Destroy hierarchy function powercap/dtpm: Fixup kfree for virtual node powercap/dtpm_cpu: Reset per_cpu variable in the release function powercap/dtpm: Change locking scheme rockchip/soc/drivers: Add DTPM description for rk3399 powercap/drivers/dtpm: Add dtpm devfreq with energy model support powercap/drivers/dtpm: Add CPU DT initialization support powercap/drivers/dtpm: Add hierarchy creation powercap/drivers/dtpm: Convert the init table section to a simple array
2022-02-24soc/tegra: fuse: Explicitly cast to/from __iomemThierry Reding1-2/+2
sparse is picky about casts between different address spaces. A cast to plain void * needs to be accompanied by a __force modifier and casting back to void __iomem * needs to be explicit to avoid warnings. Reported-by: kernel test robot <lkp@intel.com> Fixes: 88724b78a84c ("soc/tegra: fuse: Use resource-managed helpers") Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc/tegra: fuse: Update nvmem cell listkartik1-1/+19
Update tegra_fuse_cells with below entries: - gcplex-config-fuse: Configuration bits for GPU, used to enable/disable write protected region used for storing GPU firmware. - pdi0: Unique per chip public identifier. - pdi1: Unique per chip public identifier. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30Dmitry Osipenko1-2/+2
All device drivers got runtime PM and OPP support. Flip the core domain support status for Tegra20 and Tegra30 SoCs. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc: renesas: Kconfig: Introduce ARCH_RZG2L config optionLad Prabhakar1-4/+7
The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP blocks for which drivers are common. To avoid updating the Kconfig files for drivers in common to each SoC, introduce the ARCH_RZG2L config option. The ARCH_RZG2L config option will be selected by the above mentioned SoCs, and the ARCH_RZG2L config option will be used as a dependency for the drivers in common. While at it, move PM and PM_GENERIC_DOMAINS under the ARCH_RZG2L config option instead of keeping it for individual SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220224092114.25737-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-23soc: qcom: mdt_loader: Fix split-firmware conditionBjorn Andersson1-1/+1
The updated condition checking if a segment can be found in the loaded firmware blob, or need to be loaded from a separate file, incorrectly classifies segments that ends at the end of the loaded blob. The result is that the mdt loader attempts to load the segment from a separate file. Correct the conditional to use the loaded segment instead. Fixes: ea90330fa329 ("soc: qcom: mdt_loader: Extend check for split firmware") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220215034819.1209367-1-bjorn.andersson@linaro.org
2022-02-23dtpm/soc/rk3399: Add the ability to unload the moduleDaniel Lezcano1-0/+6
The dtpm hierarchy can now be removed with the dtpm_destroy_hierarchy() function. Add the module_exit() callback so the module can be unloaded by removing the previously created hierarchy. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20220130210210.549877-7-daniel.lezcano@linaro.org
2022-02-22soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configsLad Prabhakar1-0/+4
Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044 and ARCH_R9A07G054 configs. PM and PM_GENERIC_DOMAINS configs are required for RZ/{G2L,V2L} SoC without these configs the SMARC EVK's won't boot. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220221222450.5393-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21soc: imx: gpcv2: Fix clock disabling imbalance in error pathLaurent Pinchart1-1/+2
The imx_pgc_power_down() starts by enabling the domain clocks, and thus disables them in the error path. Commit 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") made the clock enable conditional, but forgot to add the same condition to the error path. This can result in a clock enable/disable imbalance. Fix it. Fixes: 18c98573a4cf ("soc: imx: gpcv2: add domain option to keep domain clocks enabled") Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-19soc: fsl: qe: Check of ioremap return valueJiasheng Jiang1-0/+2
As the possible failure of the ioremap(), the par_io could be NULL. Therefore it should be better to check it and return error in order to guarantee the success of the initiation. But, I also notice that all the caller like mpc85xx_qe_par_io_init() in `arch/powerpc/platforms/85xx/common.c` don't check the return value of the par_io_init(). Actually, par_io_init() needs to check to handle the potential error. I will submit another patch to fix that. Anyway, par_io_init() itsely should be fixed. Fixes: 7aa1aa6ecec2 ("QE: Move QE from arch/powerpc to drivers/soc") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2022-02-19soc: fsl: qe: fix typo in a commentJason Wang1-2/+2
The double `is' in the comment in line 150 is repeated. Remove one of them from the comment. Also removes a redundant tab in a new line. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2022-02-19soc: fsl: guts: Add a missing memory allocation failure checkChristophe JAILLET1-2/+7
If 'devm_kstrdup()' fails, we should return -ENOMEM. While at it, move the 'of_node_put()' call in the error handling path and after the 'machine' has been copied. Better safe than sorry. Fixes: a6fc3b698130 ("soc: fsl: add GUTS driver for QorIQ platforms") Depends-on: fddacc7ff4dd ("soc: fsl: guts: Revert commit 3c0d64e867ed") Suggested-by: Tyrel Datwyler <tyreld@linux.ibm.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2022-02-19soc: fsl: guts: Revert commit 3c0d64e867edChristophe JAILLET1-4/+3
This reverts commit 3c0d64e867ed ("soc: fsl: guts: reuse machine name from device tree"). A following patch will fix the missing memory allocation failure check instead. Suggested-by: Tyrel Datwyler <tyreld@linux.ibm.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Li Yang <leoyang.li@nxp.com>
2022-02-18Merge tag 'sound-5.17-rc5' of ↵Linus Torvalds1-11/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "A collection of small patches, mostly for old and new regressions and device-specific fixes. - Regression fixes regarding ALSA core SG-buffer helpers - Regression fix for Realtek HD-audio mutex deadlock - Regression fix for USB-audio PM resume error - More coverage of ASoC core control API notification fixes - Old regression fixes for HD-audio probe mask - Fixes for ASoC Realtek codec work handling - Other device-specific quirks / fixes" * tag 'sound-5.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (24 commits) ASoC: intel: skylake: Set max DMA segment size ASoC: SOF: hda: Set max DMA segment size ALSA: hda: Set max DMA segment size ALSA: hda/realtek: Fix deadlock by COEF mutex ALSA: usb-audio: Don't abort resume upon errors ALSA: hda: Fix missing codec probe on Shenker Dock 15 ALSA: hda: Fix regression on forced probe mask option ALSA: hda/realtek: Add quirk for Legion Y9000X 2019 ALSA: usb-audio: revert to IMPLICIT_FB_FIXED_DEV for M-Audio FastTrack Ultra ASoC: wm_adsp: Correct control read size when parsing compressed buffer ASoC: qcom: Actually clear DMA interrupt register for HDMI ALSA: memalloc: invalidate SG pages before sync ALSA: memalloc: Fix dma_need_sync() checks MAINTAINERS: update cros_ec_codec maintainers ASoC: rt5682: do not block workqueue if card is unbound ASoC: rt5668: do not block workqueue if card is unbound ASoC: rt5682s: do not block workqueue if card is unbound ASoC: tas2770: Insert post reset delay ASoC: Revert "ASoC: mediatek: Check for error clk pointer" ASoC: amd: acp: Set gpio_spkr_en to None for max speaker amplifer in machine driver ...
2022-02-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2-5/+4
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-02-14Merge tag 'asoc-fix-v5.17-rc4' of ↵Takashi Iwai1-11/+4
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus ASoC: Fixes for v5.18 More fixes that have arrived in the past few -rcs, plus a MAINTAINERS update. The biggest update here is the fix for control change notifications in ASoC generic controls found by mixer-test.
2022-02-12soc: ixp4xx-npe: Access syscon regs using regmapLinus Walleij2-9/+25
If we access the syscon (expansion bus config registers) using the syscon regmap instead of relying on direct accessor functions, we do not need to call this static code in the machine (arch/arm/mach-ixp4xx/common.c) which makes things less dependent on custom machine-dependent code. Look up the syscon regmap and handle the error: this will make deferred probe work with relation to the syscon. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220211223238.648934-8-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-02-11soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrlLucas Stach1-0/+66
This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to avoid putting more of this functionality into the decoder driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-11soc: qcom: llcc: Add configuration data for SM8450 SoCSai Prakash Ranjan1-0/+34
Add LLCC configuration data for SM8450 SoC. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/fec944cb8f2a4a70785903c6bfec629c6f31b6a4.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: llcc: Update register offsets for newer LLCC HWSai Prakash Ranjan1-7/+29
Newer LLCC HW have different register offsets for several registers, currently of which LLCC hardware info and status are used to identify the LLCC version information and other data. So use separate table to keep track of these register offsets which vary by different LLCC HW versions and eases any future addition in variations of register offsets for newer hardware. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/c655d16d945aef2d7fc8e7c212f3e1c58a84eb95.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: llcc: Add missing llcc configuration dataSai Prakash Ranjan1-0/+4
Add missing llcc configuration data for few chipsets which were not added during initial post. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/143d11bacaca086406fdd10fc32f91eccd943527.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: llcc: Add write-cache cacheable supportSai Prakash Ranjan1-0/+15
Newer SoCs with LLCC IP version 2.1.0.0 and later support write sub-cache cacheable feature. Use a separate llcc_slice_config member "write_scid_cacheable_en" to identify this feature and program LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/83372c8178f579d055ec58212ce5af5d55abadd4.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: llcc: Update the logic for version info extractionSai Prakash Ranjan1-4/+5
LLCC HW version info is made up of major, branch, minor and echo version bits each of which are 8bits. Several features in newer LLCC HW are based on the full version rather than just major or minor versions such as write-subcache enable which is applicable for versions v2.0.0.0 and later, also upcoming write-subcache cacheable for SM8450 SoC which is only present in versions v2.1.0.0 and later, so it makes it easier and cleaner to just directly compare with the full version than adding additional major/branch/ minor/echo version checks. So remove the earlier major version check and add full version check for those features. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/a82d7c32348c51fcc2b63e220d91b318bf706c83.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: llcc: Add support for 16 ways of allocationHuang Yiwei1-2/+2
Add support for 16 ways of allocation for LLCC HW version 2.1.0 and later. Signed-off-by: Huang Yiwei <hyiwei@codeaurora.org> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/a7a5f64259c2c02628f03fb59b91e9fa78da2dfb.1643355594.git.quic_saipraka@quicinc.com
2022-02-11soc: qcom: socinfo: Add some more PMICs and SoCsBjorn Andersson1-0/+12
Add SM8350, SC8280XP, SA8540P and one more SM8450 and various PMICs found on boards on these platforms to the socinfo driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220210051043.748275-1-bjorn.andersson@linaro.org
2022-02-09soc: fsl: dpio: read the consumer index from the cache inhibited areaIoana Ciornei1-4/+4
Once we added support in the dpaa2-eth for driver level software TSO we observed the following situation: if the EQCR CI (consumer index) is read from the cache-enabled area we sometimes end up with a computed value of available enqueue entries bigger than the size of the ring. This eventually will lead to the multiple enqueue of the same FD which will determine the same FD to end up on the Tx confirmation path and the same skb being freed twice. Just read the consumer index from the cache inhibited area so that we avoid this situation. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-08ASoC: Revert "ASoC: mediatek: Check for error clk pointer"Guenter Roeck1-11/+4
This reverts commit 9de2b9286a6d ("ASoC: mediatek: Check for error clk pointer"). With this patch in the tree, Chromebooks running the affected hardware no longer boot. Bisect points to this patch, and reverting it fixes the problem. An analysis of the code with this patch applied shows: ret = init_clks(pdev, clk); if (ret) return ERR_PTR(ret); ... for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { struct clk *c = clk[data->clk_id[j]]; if (IS_ERR(c)) { dev_err(&pdev->dev, "%s: clk unavailable\n", data->name); return ERR_CAST(c); } scpd->clk[j] = c; } Not all clocks in the clk_names array have to be present. Only the clocks in the data->clk_id array are actually needed. The code already checks if the required clocks are available and bails out if not. The assumption that all clocks have to be present is wrong, and commit 9de2b9286a6d ("ASoC: mediatek: Check for error clk pointer") needs to be reverted. Cc: Jiasheng Jiang <jiasheng@iscas.ac.cn> Cc: Mark Brown <broonie@kernel.org> Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Reported-by: Frank Wunderlich <frank-w@public-files.de> Reported-by: Daniel Golle <daniel@makrotopia.org> Fixes: 9de2b9286a6d ("ASoC: mediatek: Check for error clk pointer") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220207160923.3911501-1-linux@roeck-us.net Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-08soc: aspeed: lpc-ctrl: Block error printing on probe defer casesJae Hyun Yoo1-4/+3
Add a checking code when it gets -EPROBE_DEFER while getting a clock resource. In this case, it doesn't need to print out an error message because the probing will be re-visited. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Iwona Winiarska <iwona.winiarska@intel.com> Link: https://lore.kernel.org/r/20211104173709.222912-1-jae.hyun.yoo@intel.com Link: https://lore.kernel.org/r/20220201070118.196372-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-08soc: renesas: Add support for reading product revision for RZ/G2L familyBiju Das1-22/+33
As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates product revision. Use this information to populate the revision info for RZ/G2L family. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220121014117.21248-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-04rockchip/soc/drivers: Add DTPM description for rk3399Daniel Lezcano3-0/+68
The DTPM framework does support now the hierarchy description. The platform specific code can call the hierarchy creation function with an array of struct dtpm_node pointing to their parent. This patch provides a description of the big / Little CPUs and the GPU and tie them together under a virtual 'package' name. Only rk3399 is described now. The description could be extended in the future with the memory controller with devfreq. The description is always a module and it describes the soft dependencies. The userspace has to load the softdeps module in the right order. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by; Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220128163537.212248-6-daniel.lezcano@linaro.org
2022-02-04soc: qcom: mdt_loader: Extract PAS operationsBjorn Andersson1-36/+74
Rather than passing a boolean to indicate if the PAS operations should be performed from within __mdt_load(), extract them to their own helper function. This will allow clients to invoke this directly, with some qcom_scm_pas_metadata context that they later needs to release, without further having to complicate the prototype of qcom_mdt_load(). Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-9-bjorn.andersson@linaro.org
2022-02-04soc: qcom: mdt_loader: Always invoke PAS mem_setupBjorn Andersson1-11/+8
After spelunking various old kernel trees no finds has been found indicating that the PAS mem_setup call should actually be made conditional on the image being relocatable. Group the two PAS operations together, to facilitate splitting them out in a following patch. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-8-bjorn.andersson@linaro.org
2022-02-04soc: qcom: mdt_loader: Reorder parts of __qcom_mdt_load()Bjorn Andersson1-16/+16
Move the traversal of the program headers to the start of the function, to make sure that min_ and max_addr are in scope as the call to qcom_scm_pas_mem_setup() is moved in the next commit. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220128025513.97188-7-bjorn.andersson@linaro.org
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