index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
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tree
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path:
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/
drivers
/
soc
/
sifive
Age
Commit message (
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Author
Files
Lines
2022-12-27
soc: sifive: ccache: Add StarFive JH7110 support
Emil Renner Berthing
1
-1
/
+1
2022-11-10
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
Yang Yingliang
1
-4
/
+11
2022-11-10
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_in...
Yang Yingliang
1
-1
/
+4
2022-11-10
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
Yang Yingliang
1
-4
/
+11
2022-10-13
soc: sifive: ccache: define the macro for the register shifts
Zong Li
1
-5
/
+11
2022-10-13
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
Ben Dooks
1
-7
/
+10
2022-10-13
soc: sifive: ccache: reduce printing on init
Ben Dooks
1
-14
/
+11
2022-10-13
soc: sifive: ccache: determine the cache level from dts
Zong Li
1
-1
/
+5
2022-10-13
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
Greentime Hu
4
-241
/
+249
2021-01-08
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
Yash Shah
1
-3
/
+24
2020-05-29
soc: sifive: l2 cache: Mark l2_get_priv_group as static
Palmer Dabbelt
1
-1
/
+1
2020-05-29
soc: sifive: l2 cache: Eliminate an unsigned zero compare warning
Palmer Dabbelt
1
-1
/
+1
2020-05-21
riscv: Add support to determine no. of L2 cache way enabled
Yash Shah
1
-0
/
+38
2020-01-12
riscv: move sifive_l2_cache.h to include/soc
Yash Shah
1
-1
/
+1
2019-12-20
riscv: move sifive_l2_cache.c to drivers/soc
Christoph Hellwig
3
-0
/
+191