starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2020-05-29	soc: sifive: l2 cache: Mark l2_get_priv_group as static	Palmer Dabbelt	1	-1/+1
	The kbuild test robot is firing a warning over a missing prototype. The function can just be static. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-29	soc: sifive: l2 cache: Eliminate an unsigned zero compare warning	Palmer Dabbelt	1	-1/+1
	GCC warns about this comparison, which is unnecessary. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-21	riscv: Add support to determine no. of L2 cache way enabled	Yash Shah	1	-0/+38
	In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-01-12	riscv: move sifive_l2_cache.h to include/soc	Yash Shah	1	-1/+1
	The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-12-20	riscv: move sifive_l2_cache.c to drivers/soc	Christoph Hellwig	3	-0/+191
	The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>