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2023-09-25reset: starfive: jh7110: Drop the unused EXPORT_SYMBOL_GPLHal Feng1-1/+0
reset_starfive_jh7110_generic_probe() is never called by other modules, so drop the EXPORT_SYMBOL_GPL for it. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-05-31driver:reset: add reset driver for jh7110shanlong.li5-0/+284
add reset driver for jh7110 Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2023-02-01reset: uniphier-glue: Fix possible null-ptr-derefHui Tang1-3/+1
[ Upstream commit 3a2390c6777e3f6662980c6cfc25cafe9e4fef98 ] It will cause null-ptr-deref when resource_size(res) invoked, if platform_get_resource() returns NULL. Fixes: 499fef09a323 ("reset: uniphier: add USB3 core reset control") Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221114004958.258513-1-tanghui20@huawei.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-02-01reset: ti-sci: honor TI_SCI_PROTOCOL setting when not COMPILE_TESTRandy Dunlap1-1/+1
[ Upstream commit 13678f3feb3009b23aab424864fd0dac0765c83e ] There is a build error when COMPILE_TEST=y, TI_SCI_PROTOCOL=m, and RESET_TI_SCI=y: drivers/reset/reset-ti-sci.o: in function `ti_sci_reset_probe': reset-ti-sci.c:(.text+0x22c): undefined reference to `devm_ti_sci_get_handle' Fix this by making RESET_TI_SCI honor the Kconfig setting of TI_SCI_PROTOCOL when COMPILE_TEST is not set. When COMPILE_TEST is set, TI_SCI_PROTOCOL must be disabled (=n). Fixes: a6af504184c9 ("reset: ti-sci: Allow building under COMPILE_TEST") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <kristo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221030055636.3139-1-rdunlap@infradead.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-10-08Merge tag 'clk-for-linus' of ↵Linus Torvalds3-1/+165
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
2022-10-06Merge tag 'arm-drivers-6.1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "The drivers branch for 6.1 is a bit larger than for most releases. Most of the changes come from SoC maintainers for the drivers/soc subsystem: - A new driver for error handling on the NVIDIA Tegra 'control backbone' bus. - A new driver for Qualcomm LLCC/DDR bandwidth measurement - New Rockchip rv1126 and rk3588 power domain drivers - DT binding updates for memory controllers, older Rockchip SoCs, various Mediatek devices, Qualcomm SCM firmware - Minor updates to Hisilicon LPC bus, the Allwinner SRAM driver, the Apple rtkit firmware driver, Tegra firmware - Minor updates for SoC drivers (Samsung, Mediatek, Renesas, Tegra, Qualcomm, Broadcom, NXP, ...) There are also some separate subsystem with downstream maintainers that merge updates this way: - Various updates and new drivers in the memory controller subsystem for Mediatek and Broadcom SoCs - Small set of changes in preparation to add support for FF-A v1.1 specification later, in the Arm FF-A firmware subsystem - debugfs support in the PSCI firmware subsystem" * tag 'arm-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (149 commits) ARM: remove check for CONFIG_DEBUG_LL_SER3 firmware/psci: Add debugfs support to ease debugging firmware/psci: Print a warning if PSCI doesn't accept PC mode dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support soc: sunxi: sram: Add support for the D1 system control soc: sunxi: sram: Export the LDO control register soc: sunxi: sram: Save a pointer to the OF match data soc: sunxi: sram: Return void from the release function soc: apple: rtkit: Add apple_rtkit_poll soc: imx: add i.MX93 media blk ctrl driver soc: imx: add i.MX93 SRC power domain driver soc: imx: imx8m-blk-ctrl: Use genpd_xlate_onecell soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR soc: imx: add icc paths for i.MX8MP hsio/hdmi blk ctrl soc: imx: add icc paths for i.MX8MP media blk ctrl ...
2022-09-22reset: npcm: fix iprst2 and iprst4 settingTomer Maimon1-1/+1
In NPCM8XX USB reset sequence, iprst2 register was set with iprst4 value and iprst4 register wasn´t set. This fix sets the correct IP reset values in iprst2 and iprst4 registers in NPCM8XX USB reset sequence. Fixes: fc5d2a2f4aa5 ("reset: npcm: Add NPCM8XX support") Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220922153856.23326-1-tmaimon77@gmail.com
2022-09-14reset: add polarfire soc reset supportConor Dooley3-1/+165
Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
2022-08-30reset: microchip-sparx5: issue a reset on startupMichael Walle1-5/+17
Originally this was used in by the switch core driver to issue a reset. But it turns out, this isn't just a switch core reset but instead it will reset almost the complete SoC. Instead of adding almost all devices of the SoC a shared reset line, issue the reset once early on startup. Keep the reset controller for backwards compatibility, but make the actual reset a noop. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Steen Hegelund <Steen.Hegelund@microchip.com> on Sparx5 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220826115607.1148489-2-michael@walle.cc
2022-08-30reset: imx7: Fix the iMX8MP PCIe PHY PERST supportRichard Zhu1-0/+1
On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here. Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1661845564-11373-5-git-send-email-hongxing.zhu@nxp.com
2022-08-15arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCAWilliam Zhang1-1/+1
With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Guenter Roeck <linux@roeck-us.net> (for watchdog) Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci) Acked-by: Wolfram Sang <wsa@kernel.org> (for i2c) Acked-by: Philipp Zabel <p.zabel@pengutronix.de> (for reset) Link: https://lore.kernel.org/r/20220803175455.47638-7-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-08-05Merge tag 'arm-late-6.0' of ↵Linus Torvalds3-2/+138
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These updates came in after I had already tagged the branches, but they still seem appropriate for 6.0 and most of them were part of linux-next through other trees. - The reset controller tree adds one new driver for the TI TPS380x power management chip and a few minor changes in other drivers - Apple M1 now has a DT entry for the NVMe controller after the driver was merged, and has a new mailing list in the MAINTAINERS file. - Fixes for USB on the Socionext Uniphier platforms and the network controller on Intel Cyclone5" * tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: uniphier: Fix USB interrupts for PXs3 SoC ARM: dts: uniphier: Fix USB interrupts for PXs2 SoC arm64: dts: apple: t8103: Add ANS2 NVMe nodes reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" reset: tps380x: Add TPS380x device driver supprt dt-bindings: reset: Add TPS380x documentation dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G2UL USBPHY Control bindings ARM: dts: add EMAC AXI settings for Cyclone5 reset: reset-simple should depends on HAS_IOMEM Revert "reset: microchip-sparx5: allow building as a module" reset: a10sr: allow building under COMPILE_TEST reset: allow building of reset simple driver if expert config selected reset: microchip-sparx5: allow building as a module arm64: dts: apple: Re-parent ANS2 power domains MAINTAINERS: add ARM/APPLE MACHINE mailing list
2022-08-04Merge tag 'spdx-6.0-rc1' of ↵Linus Torvalds2-18/+2
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx Pull SPDX updates from Greg KH: "Here is the set of SPDX comment updates for 6.0-rc1. Nothing huge here, just a number of updated SPDX license tags and cleanups based on the review of a number of common patterns in GPLv2 boilerplate text. Also included in here are a few other minor updates, two USB files, and one Documentation file update to get the SPDX lines correct. All of these have been in the linux-next tree for a very long time" * tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits) Documentation: samsung-s3c24xx: Add blank line after SPDX directive x86/crypto: Remove stray comment terminator treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE ...
2022-07-28reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage"Colin Ian King1-1/+1
There is a spelling mistake in the MODULE_DESCRIPTION text. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220728110554.18320-1-colin.i.king@gmail.com
2022-07-27reset: tps380x: Add TPS380x device driver supprtMarco Felsch3-0/+135
The TI TPS380x family [1] is a voltage supervisor with a dedicated manual reset (mr) line input and a reset output. The chip(s) have a build in reset delay, depending on the chip partnumber. This simple driver addresses this so the cosumer don't need to care about it. [1] https://www.ti.com/product/TPS3801 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> [p.zabel@pengutronix.de: drop Todo comment about min/typ/max reset time] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220530092226.748644-2-m.felsch@pengutronix.de
2022-07-20reset: reset-simple should depends on HAS_IOMEMBen Dooks1-0/+1
The reset-simple driver does not build on all architecuters as it requires devm_ioremap_resource() which is only built when CONFIG_HAS_IOMEM is enabled in the kenrel. Fix the following error by depending on CONFIG_HAS_IOMEM: drivers/reset/reset-simple.o: in function `reset_simple_probe': reset-simple.c:(.text+0x3aa): undefined reference to `devm_ioremap_resource' Fixes: 18d1909be345 ("reset: allow building of reset simple driver if expert config selected") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220719085200.203688-1-ben.dooks@sifive.com
2022-07-19Merge branch 'nuvoton/newsoc' into arm/newsocArnd Bergmann1-34/+173
Merge the new SoC support from Tomer Maimon: "This patchset adds initial support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family. The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. The NPCM8XX computing subsystem comprises a quadcore ARM Cortex A35 ARM-V8 architecture. This patchset adds minimal architecture and drivers such as: Clocksource, Clock, Reset, and WD. Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. This patchset was tested on the Arbel NPCM8XX evaluation board." I'm leaving out the clk controller driver, which is still under review. * nuvoton/newsoc: arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string
2022-07-19reset: npcm: Add NPCM8XX supportTomer Maimon1-38/+173
Updated the NPCM reset driver to add support for Nuvoton BMC NPCM8XX SoC. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Add NPCM8XX USB reset. - Add data to handle architecture-specific reset parameters. - Some of the Reset Id and number of resets are different from NPCM7XX. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-19reset: npcm: using syscon instead of device dataTomer Maimon1-5/+9
Using syscon device tree property instead of device data to handle the NPCM general control registers. In case the syscon not found the code still search for nuvoton,npcm750-gcr to support DTS backward compatibility. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-13Revert "reset: microchip-sparx5: allow building as a module"Philipp Zabel2-3/+7
This reverts commit b6b9585876da018bdde2d5f15d206a689c0d70f3. This breaks MDIO on kswitch-d10, presumably because the global switch reset is not released early enough anymore. Reported-by: Michael Walle <michael@walle.cc> Cc: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220713084010.168720-1-p.zabel@pengutronix.de
2022-07-11reset: a10sr: allow building under COMPILE_TESTPhilipp Zabel1-1/+1
This driver can be built under COMPILE_TEST. Allow it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220711130624.1217599-1-p.zabel@pengutronix.de
2022-07-11reset: allow building of reset simple driver if expert config selectedBen Dooks1-1/+1
If CONFIG_EXPERT is selected, allow selection of CONFIG_RESET_SIMPLE if needed by the user. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220708165656.269507-1-ben.dooks@sifive.com
2022-07-08reset: Add Sunplus SP7021 reset driverQin Jian3-0/+222
Add reset driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-06-29reset: microchip-sparx5: allow building as a moduleClément Léger2-7/+3
Set RESET_MCHP_SPARX5 as a tristate and add MODULE_DEVICE_TABLE() to allow building this driver as a module. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220617103730.490588-1-clement.leger@bootlin.com
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULEThomas Gleixner2-18/+2
Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-05-10Merge tag 'ti-driver-soc-for-v5.19' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers TI Driver updates for v5.19 * wkup_m3: io isolation, voltage scaling, vtt regulator and a debug option to stop m3 in suspend. * tisci: support for polled mode for system suspend, reset driver is now enabled for COMPILE_TEST * knav, dma.. misc cleanups for IS_ERR, pm_run_time*, and various other fixups. * tag 'ti-driver-soc-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: wkup_m3_ipc: Add debug option to halt m3 in suspend soc: ti: wkup_m3_ipc: Add support for i2c voltage scaling soc: ti: wkup_m3_ipc: Add support for IO Isolation soc: ti: knav_qmss_queue: Use IS_ERR instead of IS_ERR_OR_NULL when checking knav_queue_open() result soc: ti: pm33xx: using pm_runtime_resume_and_get instead of pm_runtime_get_sync firmware: ti_sci: Switch transport to polled mode during system suspend soc: ti: wkup_m3_ipc: Add support for toggling VTT regulator soc: ti: knav_qmss_queue: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync soc: ti: knav_dma: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync reset: ti-sci: Allow building under COMPILE_TEST soc: ti: ti_sci_pm_domains: Check for null return of devm_kcalloc soc: ti: omap_prm: Use of_device_get_match_data() soc: ti: pruss: using pm_runtime_resume_and_get instead of pm_runtime_get_sync soc: ti: replace usage of found with dedicated list iterator variable soc: ti: wkup_m3_ipc: fix platform_get_irq.cocci warning Link: https://lore.kernel.org/r/20220507163424.pvqnwrxpoo73lmp2@debtless Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-05Merge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into ↵Arnd Bergmann5-43/+56
arm/drivers Reset controller updates for v5.19 Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC reset controller support to reset-simple, and R9A07G054 USBPHY reset controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to device_reset(), simplify the uniphier-glue reset driver using bulk API and devres and clean up its dt-bindings docs. Convert most dt-bindings docs from txt to yaml. * tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux: dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml dt-bindings: reset: lantiq,reset: Convert to yaml dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml dt-bindings: reset: berlin: Convert to yaml dt-bindings: reset: ath79: Convert to yaml dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L reset: ACPI reset support reset: simple: Add AST2600 compatible reset: reset-meson: add support for the Meson-S4 SoC Reset Controller dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller dt-bindings: reset: Add compatible for Meson-S4 Reset Controller reset: uniphier-glue: Use devm_add_action_or_reset() reset: uniphier-glue: Use reset_control_bulk API Link: https://lore.kernel.org/r/20220503160057.46625-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-03reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2LLad Prabhakar1-1/+1
The USBPHY Control block is identical on Renesas RZ/G2L and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220406071647.14037-1-prabhakar.mahadev-lad.rj@bp.renesas.com
2022-05-03reset: ACPI reset supportKrishna Yarlagadda1-1/+14
Some of the IO devices like I2C or SPI require reset at runtime to recover from an error condition without changing the power state of the system. Added check for ACPI handle and a call to method '__RST' if supported. Devices using device tree method are unaffected by this. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> [p.zabel@pengutronix.de: wrap in #ifdef CONFIG_ACPI due to missing stubs] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220307135626.16673-1-kyarlagadda@nvidia.com
2022-05-03reset: simple: Add AST2600 compatibleJoel Stanley1-0/+1
Similar to the 2400 and 2500, the LPC controller has some simple reset lines that are used by the UART devices. This is already documented in LPC bindings document. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220221072650.129348-1-joel@jms.id.au
2022-05-03reset: reset-meson: add support for the Meson-S4 SoC Reset ControllerZelong Dong1-0/+6
Compared to the A1 SoCs the number of RESET registers is different and the offset for the level registers is the same. Add a new compatible string and struct meson_reset_param to add support for the reset controller on the S4 SoC. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220107023931.13251-4-zelong.dong@amlogic.com
2022-05-03reset: uniphier-glue: Use devm_add_action_or_reset()Philipp Zabel1-26/+24
Slightly simplify uniphier_glue_reset_probe() and drop uniphier_glue_reset_remove() by using devm_add_action_or_reset() for clock and reset cleanup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20211215093829.3209416-2-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-05-03reset: uniphier-glue: Use reset_control_bulk APIPhilipp Zabel1-19/+14
This driver already uses the clk_bulk API. Simplify the driver by using the reset_control_bulk API as well. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20211215093829.3209416-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-04-15reset: ti-sci: Allow building under COMPILE_TESTPhilipp Zabel1-1/+1
Since commit 043cfff99a18 ("firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined") it is possible to build reset-ti-sci under CONFIG_COMPILE_TEST. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220404094500.2708816-1-p.zabel@pengutronix.de
2022-04-04reset: tegra-bpmp: Restore Handle errors in BPMP responseSameer Pujar1-1/+8
This reverts following commit 69125b4b9440 ("reset: tegra-bpmp: Revert Handle errors in BPMP response"). The Tegra194 HDA reset failure is fixed by commit d278dc9151a0 ("ALSA: hda/tegra: Fix Tegra194 HDA reset failure"). The temporary revert of original commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP response") can be removed now. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1641995806-15245-1-git-send-email-spujar@nvidia.com
2022-04-04reset: renesas: Check return value of reset_control_deassert()Heiner Kallweit1-1/+3
Deasserting the reset is vital, therefore bail out in case of error. Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/b2131908-0110-006b-862f-080517f3e2d8@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-02-25reset: Add Delta TN48M CPLD reset controllerRobert Marko3-0/+142
Delta TN48M CPLD exposes resets for the following: * 88F7040 SoC * 88F6820 SoC * 98DX3265 switch MAC-s * 88E1680 PHY-s * 88E1512 PHY * PoE PSE controller Controller supports only self clearing resets. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20220131133049.77780-5-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-01-10Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds3-0/+181
Pull RISC-V SoC updates from Arnd Bergmann: "Add support for StarFive JH7100 RISC-V SoC This adds support for the StarFive JH7100, including the necessary device drivers and DT files for the BeagleV Starlight prototype board, with additional boards to be added later. This SoC promises to be the first usable low-cost platform for RISC-V. I've taken this through the SoC tree in the anticipation of adding a few other Arm based SoCs as well, but those did not pass the review in time, so it's only this one" * tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: reset: starfive-jh7100: Fix 32bit compilation RISC-V: Add BeagleV Starlight Beta device tree RISC-V: Add initial StarFive JH7100 device tree serial: 8250_dw: Add StarFive JH7100 quirk dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts pinctrl: starfive: Add pinctrl driver for StarFive SoCs dt-bindings: pinctrl: Add StarFive JH7100 bindings dt-bindings: pinctrl: Add StarFive pinctrl definitions reset: starfive-jh7100: Add StarFive JH7100 reset driver dt-bindings: reset: Add Starfive JH7100 reset bindings dt-bindings: reset: Add StarFive JH7100 reset definitions clk: starfive: Add JH7100 clock generator driver dt-bindings: clock: starfive: Add JH7100 bindings dt-bindings: clock: starfive: Add JH7100 clock definitions dt-bindings: interrupt-controller: Add StarFive JH7100 plic dt-bindings: timer: Add StarFive JH7100 clint RISC-V: Add StarFive SoC Kconfig option
2021-12-20reset: starfive-jh7100: Fix 32bit compilationEmil Renner Berthing1-0/+1
We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't be defined when compiling on 32bit architectures: On i386: ../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’: ../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration] value = readq(reg_assert); ^~~~~ ../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration] writeq(value, reg_assert); ^~~~~~ On m68k: drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration] drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1 make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2 make[1]: *** [Makefile:1969: drivers] Error 2 make: *** [Makefile:226: __sub-make] Error 2 Fixes: 0be3a1595bf8 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20211220121800.760846-1-kernel@esmil.dk' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16reset: starfive-jh7100: Add StarFive JH7100 reset driverEmil Renner Berthing3-0/+180
Add a driver for the StarFive JH7100 reset controller. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-15reset: renesas: Fix Runtime PM usageHeiner Kallweit1-1/+6
If pm_runtime_resume_and_get() fails then it returns w/o the RPM usage counter being incremented. In this case call pm_runtime_put() in remove() will result in a usage counter imbalance. Therefore check the return code of pm_runtime_resume_and_get() and bail out in case of error. Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver") Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/ec24e13f-0530-b091-7a08-864577b9b3be@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-11-17reset: tegra-bpmp: Revert Handle errors in BPMP responseJon Hunter1-8/+1
Commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP response") fixed an issue in the Tegra BPMP error handling but has exposed an issue in the Tegra194 HDA driver and now resetting the Tegra194 HDA controller is failing. For now revert the commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP response") while a fix for the Tegra HDA driver is created. Fixes: c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP response") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20211112112712.21587-1-jonathanh@nvidia.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-11-04Merge tag 'drivers-5.16' of ↵Linus Torvalds4-10/+65
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "These are all the driver updates for SoC specific drivers. There are a couple of subsystems with individual maintainers picking up their patches here: - The reset controller subsystem add support for a few new SoC variants to existing drivers, along with other minor improvements - The OP-TEE subsystem gets a driver for the ARM FF-A transport - The memory controller subsystem has improvements for Tegra, Mediatek, Renesas, Freescale and Broadcom specific drivers. - The tegra cpuidle driver changes get merged through this tree this time. There are only minor changes, but they depend on other tegra driver updates here. - The ep93xx platform finally moves to using the drivers/clk/ subsystem, moving the code out of arch/arm in the process. This depends on a small sound driver change that is included here as well. - There are some minor updates for Qualcomm and Tegra specific firmware drivers. The other driver updates are mainly for drivers/soc, which contains a mixture of vendor specific drivers that don't really fit elsewhere: - Mediatek drivers gain more support for MT8192, with new support for hw-mutex and mmsys routing, plus support for reset lines in the mmsys driver. - Qualcomm gains a new "sleep stats" driver, and support for the "Generic Packet Router" in the APR driver. - There is a new user interface for routing the UARTS on ASpeed BMCs, something that apparently nobody else has needed so far. - More drivers can now be built as loadable modules, in particular for Broadcom and Samsung platforms. - Lots of improvements to the TI sysc driver for better suspend/resume support" Finally, there are lots of minor cleanups and new device IDs for amlogic, renesas, tegra, qualcomm, mediateka, samsung, imx, layerscape, allwinner, broadcom, and omap" * tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (179 commits) optee: Fix spelling mistake "reclain" -> "reclaim" Revert "firmware: qcom: scm: Add support for MC boot address API" qcom: spm: allow compile-testing firmware: arm_ffa: Remove unused 'compat_version' variable soc: samsung: exynos-chipid: add exynosautov9 SoC support firmware: qcom: scm: Don't break compile test on non-ARM platforms soc: qcom: smp2p: Add of_node_put() before goto soc: qcom: apr: Add of_node_put() before return soc: qcom: qcom_stats: Fix client votes offset soc: qcom: rpmhpd: fix sm8350_mxc's peer domain dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226 firmware: qcom: scm: Add support for MC boot address API soc: qcom: spm: Add 8916 SPM register data dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu soc: qcom: socinfo: Add PM8150C and SMB2351 models firmware: qcom_scm: Fix error retval in __qcom_scm_is_call_available() soc: aspeed: Add UART routing support soc: fsl: dpio: rename the enqueue descriptor variable soc: fsl: dpio: use an explicit NULL instead of 0 ...
2021-10-18reset: mchp: sparx5: Extend support for lan966xHoratiu Vultur2-9/+33
This patch extends sparx5 driver to support also the lan966x. The process to reset the switch is the same only it has different offsets. Therefore make the driver more generic and add support for lan966x. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20211018091522.1113510-3-horatiu.vultur@microchip.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: socfpga: add empty driver allowing consumers to probePaweł Anikiel1-0/+26
The early reset driver doesn't ever probe, which causes consuming devices to be unable to probe. Add an empty driver to set this device as available, allowing consumers to probe. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Link: https://lore.kernel.org/r/20210920124141.1166544-4-pan@semihalf.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: uniphier: Add NX1 reset supportKunihiko Hayashi2-0/+29
Add basic reset data for UniPhier NX1 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633399842-1402-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: uniphier: Add audio system and video input reset control for PXs3Kunihiko Hayashi1-0/+2
Add reset lines for audio subsystem (AIO) and video input subsystem (EXIV) on UniPhier PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633399842-1402-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: Allow building Broadcom STB RESCAL as moduleFlorian Fainelli1-1/+1
The driver can be built as a module and uses device managed resources. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210924030840.9650-1-f.fainelli@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: tegra-bpmp: Handle errors in BPMP responseMikko Perttunen1-1/+8
The return value from tegra_bpmp_transfer indicates the success or failure of the IPC transaction with BPMP. If the transaction succeeded, we also need to check the actual command's result code. Add code to do this. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20210915085517.1669675-2-mperttunen@nvidia.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2021-10-05reset: pistachio: Re-enable driver selectionGeert Uytterhoeven1-2/+2
After the retirement of MACH_PISTACHIO, the Pistachio Reset Driver is no longer auto-enabled when building a kernel for Pistachio systems. Worse, the driver cannot be enabled by the user at all (unless compile-testing), as the config symbol is invisible. Fix this partially by making the symbol visible again when compiling for MIPS, and dropping the useless default. The user still has to enable the driver manually when building a kernel for Pistachio systems, though. Fixes: 104f942b2832ab13 ("MIPS: Retire MACH_PISTACHIO") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rahul Bedarkar <rahulbedarkar89@gmail.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lore.kernel.org/r/2c399e52540536df9c4006e46ef93fbccdde88db.1631610825.git.geert+renesas@glider.be Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-28 22:46:05 +0300