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path: root/drivers/remoteproc/mtk_common.h
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2024-04-30remoteproc: mediatek: Support setting DRAM and IPI shared buffer sizesOlivia Wen1-3/+8
The SCP on different chips will require different DRAM sizes and IPI shared buffer sizes based on varying requirements. Signed-off-by: Olivia Wen <olivia.wen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240430011534.9587-4-olivia.wen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeoutTinghan Shen1-0/+5
The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-12-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offsetTinghan Shen1-0/+7
Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset" configuration to control the access destination of SCP core 1 to boot core 1 from different SRAM location. The "core 1 SRAM offset" configuration is composed by a range and an offset. It works like a simple memory mapped mechanism. When SCP core 1 accesses a SRAM address located in the range, the SCP bus adds the configured offset to the address to shift the physical destination address on SCP SRAM. This shifting is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-11-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on ↵Tinghan Shen1-0/+3
dual-core SCP Previously, SCP core 0 controlled the power of L2TCM and dictated that SCP core 1 could only boot after SCP core 0. To address this constraint, extracted the power control flow of L2TCM and made it shared between both cores, enabling support for arbitrary boot order. The flow for controlling L2TCM power has been incorporated into the mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are respectively invoked during the rproc->ops->start() and rproc->ops->stop() operations. These APIs effectively serve the same purpose as the rproc prepare()/unprepare() APIs." Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-10-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Probe SCP cluster on single-core SCPTinghan Shen1-0/+2
This is the 3rd preliminary step for probing multi-core SCP. Rewrite the probing flow of single-core SCP to adapt with the 'cluster' concept needed by the multi-core SCP. The SCP core object(s) is maintained at the cluster list. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-8-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Extract SCP common registersTinghan Shen1-4/+9
This is the 1st preliminary steps for probing multi-core SCP. The registers of config and l1tcm are common on single-core SCP and multi-core SCP. Extract these registers out to reduce duplicated fields in mtk_scp when multiple SCP instances are created. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-6-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2023-09-13remoteproc: mediatek: Add MT8195 SCP core 1 operationsTinghan Shen1-0/+9
The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230901080935.14571-5-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2022-04-11remoteproc: mediatek: Fix side effect of mt8195 sram power onTinghan Shen1-0/+2
The definition of L1TCM_SRAM_PDN bits on mt8195 is different to mt8192. L1TCM_SRAM_PDN bits[3:0] control the power of mt8195 L1TCM SRAM. L1TCM_SRAM_PDN bits[7:4] control the access path to EMI for SCP. These bits have to be powered on to allow EMI access for SCP. Bits[7:4] also affect audio DSP because audio DSP and SCP are placed on the same hardware bus. If SCP cannot access EMI, audio DSP is blocked too. L1TCM_SRAM_PDN bits[31:8] are not used. This fix removes modification of bits[7:4] when power on/off mt8195 SCP L1TCM. It's because the modification introduces a short period of time blocking audio DSP to access EMI. This was not a problem until we have to load both SCP module and audio DSP module. audio DSP needs to access EMI because it has source/data on DRAM. Audio DSP will have unexpected behavior when it accesses EMI and the SCP driver blocks the EMI path at the same time. Fixes: 79111df414fc ("remoteproc: mediatek: Support mt8195 scp") Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220321060340.10975-1-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2022-03-11remoteproc: mediatek: Support mt8186 scpAllen-KH Cheng1-0/+3
Add SCP support for mt8186 Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220225132747.31808-3-allen-kh.cheng@mediatek.com
2021-09-28remoteproc: mediatek: Support mt8195 scpTinghan Shen1-0/+1
The SCP clock design is changed on mt8195 that doesn't need to control SCP clock on kernel side. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20210924033935.2127-5-tinghan.shen@mediatek.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-02-09remoteproc/mediatek: support L1TCMTzung-Bi Shih1-0/+5
L1TCM is a high performance memory region in MT8192 SCP. Reads L1TCM memory region from DTS to determine if the machine supports. Loads L1TCM memory region to SCP sys if the firmware provides. Starts from MT8192 SCP, the firmware contains physical addresses for each memory region, for instance: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0xXXXXXX 0xXXXXXXXX 0x10500000 0xXXXXX 0xXXXXX XXX 0xXXXX LOAD 0xXXXXXX 0xXXXXXXXX 0x10700000 0xXXXXX 0xXXXXX XXX 0xXXXX LOAD 0xXXXXXX 0xXXXXXXXX 0x50000000 0xXXXXX 0xXXXXX XXX 0xXXXX Kernel driver can use the "PhysAddr" (i.e. da in the da_to_va callbacks) to know the ELF segment belongs to which region. To backward compatible to MT8183 SCP, separates the da_to_va callbacks for new and legacy version. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20210127083136.3745652-5-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-02-09remoteproc/mediatek: enable MPU for all memory regions in MT8192 SCPTzung-Bi Shih1-0/+1
The register MT8192_CORE0_MEM_ATT_PREDEF contains attributes for each memory region. It defines whether a memory region can be managed by MPU or not. In the past, due to the default settings in the register, MT8192 SCP works luckily. After enabling L1TCM, SCP starts to access memory region that is not included in the default settings. As a result, SCP hangs. Enables MPU for all memory regions in MT8192 SCP. Note that the register is read only once when SCP resets. Thus, it must be set from kernel side. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20210127083136.3745652-3-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-02-09remoteproc/mediatek: acknowledge watchdog IRQ after handledTzung-Bi Shih1-0/+1
Acknowledges watchdog IRQ after handled or kernel keeps receiving the interrupt. Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP") Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20210127082046.3735157-1-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-10remoteproc/mediatek: read IPI buffer offset from FWTzung-Bi Shih1-0/+2
Reads the IPI buffer offset from the FW binary. The information resides in addr of .ipi_buffer section. Moves scp_ipi_init() to rproc_ops::parse_fw() phase. The IPI buffer can be initialized only if the offset is clear. To backward compatible to MT8183 SCP, specify the offset in the board specific mtk_scp_of_data. Reads the default offset if the firmware doesn't have it. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20201202044609.2501913-1-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-10remoteproc/mediatek: change MT8192 CFG register baseTzung-Bi Shih1-13/+13
The correct MT8192 CFG register base is 0x20000 off. Changes the registers accordingly. Fixes: fd0b6c1ff85a ("remoteproc/mediatek: Add support for mt8192 SCP") Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20201210054109.587795-1-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-21remoteproc/mediatek: fix sparse errors on dma_alloc and dma_freeTzung-Bi Shih1-1/+1
Fixes the following sparse errors on dma_alloc_coherent() and dma_free_coherent(). On drivers/remoteproc/mtk_scp.c:559:23: warning: incorrect type in assignment (different address spaces) expected void [noderef] __iomem *cpu_addr got void * On drivers/remoteproc/mtk_scp.c:572:56: warning: incorrect type in argument 3 (different address spaces) expected void *cpu_addr got void [noderef] __iomem *cpu_addr The cpu_addr is not a __iomem address. Removes the marker. Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20201116082537.3287009-3-tzungbi@google.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-26remoteproc/mediatek: Add support for mt8192 SCPPi-Hsun Shih1-0/+32
Add support for mt8192 SCP. Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@google.com> Link: https://lore.kernel.org/r/20200921094847.2112399-1-pihsun@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-04-17remoteproc: mtk_scp: use dma_addr_t for DMA APIArnd Bergmann1-1/+1
dma_addr_t and phys_addr_t are distinct types and must not be mixed, as both the values and the size of the type may be different depending on what the remote device uses. In this driver the compiler warns when the two types are different: drivers/remoteproc/mtk_scp.c: In function 'scp_map_memory_region': drivers/remoteproc/mtk_scp.c:454:9: error: passing argument 3 of 'dma_alloc_coherent' from incompatible pointer type [-Werror=incompatible-pointer-types] 454 | &scp->phys_addr, GFP_KERNEL); | ^~~~~~~~~~~~~~~ | | | phys_addr_t * {aka unsigned int *} In file included from drivers/remoteproc/mtk_scp.c:7: include/linux/dma-mapping.h:642:15: note: expected 'dma_addr_t *' {aka 'long long unsigned int *'} but argument is of type 'phys_addr_t *' {aka 'unsigned int *'} 642 | dma_addr_t *dma_handle, gfp_t gfp) Change the phys_addr member to be typed and named according to how it is allocated. Fixes: 63c13d61eafe ("remoteproc/mediatek: add SCP support for mt8183") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200408155450.2186471-1-arnd@arndb.de Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-20rpmsg: add rpmsg support for mt8183 SCP.Pi-Hsun Shih1-0/+2
Add a simple rpmsg support for mt8183 SCP, that use IPI / IPC directly. Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Link: https://lore.kernel.org/r/20191112110330.179649-4-pihsun@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-20remoteproc/mediatek: add SCP support for mt8183Erin Lo1-0/+92
Provide a basic driver to control Cortex M4 co-processor Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Link: https://lore.kernel.org/r/20191112110330.179649-3-pihsun@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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