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path: root/drivers/ptp/ptp_clockmatrix.c
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2021-09-27ptp: clockmatrix: use rsmu driver to access i2c/spi busMin Li1-361/+411
rsmu (Renesas Synchronization Management Unit ) driver is located in drivers/mfd and responsible for creating multiple devices including clockmatrix phc, which will then use the exposed regmap and mutex handle to access i2c/spi bus. Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-14ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF ↵Min Li1-45/+327
and WP Also correct how initialize_dco_operating_mode is called Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-14ptp: ptp_clockmatrix: Add support for FW 5.2 (8A34005)Min Li1-86/+93
So far we don't need to support new 5.2 functions but different register addresses Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-14ptp: ptp_clockmatrix: Remove idtcm_enable_tod_sync()Min Li1-227/+2
Not need since TCS firmware file will configure it properlly. Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-13ptp: ptp_clockmatrix: Demote non-kernel-doc header to standard commentLee Jones1-2/+2
Fixes the following W=1 kernel build warning(s): drivers/ptp/ptp_clockmatrix.c:1408: warning: Cannot understand * @brief Maximum absolute value for write phase offset in picoseconds drivers/ptp/ptp_clockmatrix.c:1408: warning: Cannot understand * @brief Maximum absolute value for write phase offset in picoseconds drivers/ptp/ptp_clockmatrix.c:1408: warning: Cannot understand * @brief Maximum absolute value for write phase offset in picoseconds drivers/ptp/ptp_clockmatrix.c:1408: warning: Cannot understand * @brief Maximum absolute value for write phase offset in picoseconds drivers/ptp/ptp_clockmatrix.c:1408: warning: Cannot understand * @brief Maximum absolute value for write phase offset in picoseconds Cc: Richard Cochran <richardcochran@gmail.com> Cc: IDT-support-1588@lm.renesas.com Cc: netdev@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: clean-up - parenthesis around a == b are unnecessaryVincent Cheng1-10/+8
Code clean-up. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: Simplify code - remove unnecessary `err` variable.Vincent Cheng1-4/+1
Code clean-up. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: Coding style - tighten vertical spacing.Vincent Cheng1-79/+11
Code clean-up. * Remove blank line between variable declarations. * Remove blank line between: err = blah(...) if (err) ... * Remove unnecessary blank line before/after loop constructs. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: Clean-up dev_*() messages.Vincent Cheng1-79/+43
Code clean-up. * Remove unnecessary \n termination from dev_*() messages. * Remove 'char *fmt' to define strings to stay within 80 column limit. Not needed since coding guidelines increased to 100 columns limit. Keeping format in place allows static code checkers to validate the arguments. * Tighten up vertical spacing. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.Vincent Cheng1-3/+13
When enabling output using PTP_CLK_REQ_PEROUT, need to align the output clock to the internal 1 PPS clock. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-18ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.Vincent Cheng1-2/+62
Part of the device initialization aligns the rising edge of the output clock to the internal 1 PPS clock. If the system APLL and DPLL is not locked, then the alignment will fail and there will be a fixed offset between the internal 1 PPS clock and the output clock. After loading the device firmware, poll the system APLL and DPLL for locked state prior to initialization, timing out after 2 seconds. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-12-10ptp: clockmatrix: deprecate firmware older than 4.8.7Min Li1-30/+39
Add deprecated flag to indicate < v4.8.7. Fix idtcm_enable_tod() call correct settime(). Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-4-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-12-10ptp: clockmatrix: Fix non-zero phase_adj is lost after snapMin Li1-21/+88
Fix non-zero phase_adj is lost after snap. Use ktime_sub to do ktime_t subtraction. Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-3-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-12-10ptp: clockmatrix: remove 5 second delay before entering write phase modeMin Li1-22/+0
Remove write phase mode 5 second setup delay, not needed. Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1607442117-13661-2-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-12-10ptp: clockmatrix: reset device and check BOOT_STATUSMin Li1-34/+116
SM_RESET device only when loading full configuration and check for BOOT_STATUS. Also remove polling for write trigger done in _idtcm_settime(). Changes since v1: -Correct warnings from strict checkpatch Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1607442117-13661-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-26ptp: clockmatrix: bug fix for idtcm_strverscmpMin Li1-33/+16
Feed kstrtou8 with NULL terminated string. Changes since v1: -Use sscanf to get rid of adhoc string parse. Changes since v2: -Check if sscanf returns 3. Fixes: 7ea5fda2b132 ("ptp: ptp_clockmatrix: update to support 4.8.7 firmware") Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/1606273115-25792-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-08-20ptp: ptp_clockmatrix: use i2c_master_send for i2c writeMin Li1-13/+43
The old code for i2c write would break on some controllers, which fails at handling Repeated Start Condition. So we will just use i2c_master_send to handle write in one transanction. Changes since v1: - Remove indentation change Signed-off-by: Min Li <min.li.xe@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-31ptp: ptp_clockmatrix: update to support 4.8.7 firmwareMin Li1-198/+947
With 4.8.7 firmware, adjtime can change delta instead of absolute time, which greately increases snap accuracy. PPS alignment doesn't have to be set for every single TOD change. Other minor changes includes: adding more debug logs, increasing snap accuracy for pre 4.8.7 firmware and supporting new tcs2bin format. Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-03ptp: ptp_clockmatrix: Add adjphase() to support PHC write phase mode.Vincent Cheng1-0/+92
Add idtcm_adjphase() to support PHC write phase mode. Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-26ptp: clockmatrix: remove unnecessary comparisonYang Yingliang1-1/+1
The type of loaddr is u8 which is always '<=' 0xff, so the loaddr <= 0xff is always true, we can remove this comparison. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-08ptp: clockmatrix: Rework clockmatrix version information.Vincent Cheng1-64/+13
Simplify and fix the version information displayed by the driver. The new info better relects what is needed to support the hardware. Prev: Version: 4.8.0, Pipeline 22169 0x4001, Rev 0, Bond 5, CSR 311, IRQ 2 New: Version: 4.8.0, Id: 0x4001 Hw Rev: 5 OTP Config Select: 15 - Remove pipeline, CSR and IRQ because version x.y.z already incorporates this information. - Remove bond number because it is not used. - Remove rev number because register was not implemented, always 0 - Add HW Rev ID register to replace rev number - Add OTP config select to show the user configuration chosen by the configurable GPIO pins on start-up Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-03ptp: ptp_clockmatrix: constify copied structureJulia Lawall1-1/+1
The idtcm_caps structure is only copied into another structure, so make it const. The opportunity for this change was found using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-07ptp: ptp_clockmatrix: Fix missing unlock on error in idtcm_probe()Wei Yongjun1-1/+3
Add the missing unlock before return from function idtcm_probe() in the error handling case. Fixes: 3a6ba7dc7799 ("ptp: Add a ptp clock driver for IDT ClockMatrix.") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-04ptp: Add a ptp clock driver for IDT ClockMatrix.Vincent Cheng1-0/+1425
The IDT ClockMatrix (TM) family includes integrated devices that provide eight PLL channels. Each PLL channel can be independently configured as a frequency synthesizer, jitter attenuator, digitally controlled oscillator (DCO), or a digital phase lock loop (DPLL). Typically these devices are used as timing references and clock sources for PTP applications. This patch adds support for the device. Co-developed-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Vincent Cheng <vincent.cheng.xh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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