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2021-02-23Merge tag 'pinctrl-v5.12-1' of ↵Linus Torvalds66-13152/+8765
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.12 kernel. This time a calm set with no core changes. New drivers/subdrivers: - Renesas R8A7790A0 pin controller. - Allwinner H616 and H616-R pin controllers. - Qualcomm SM8350 and SC8180x pin controllers. Improvements: - Redo the DT bindings for Ralink RT2880. - A common Qualcomm TLMM DT binding in YAML. - Delete the unused drivers for U300, COH901, Sirf Atlas, and ZTE ZX" * tag 'pinctrl-v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt dt-bindings: pinctrl: Group tuples in pin control properties pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'" pinctrl: at91-pio4: add support for slew-rate dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: actions: Add depends on || COMPILE_TEST pinctrl: single: set function name when adding function pinctrl: qcom: Add sc8180x TLMM driver dt-bindings: pinctrl: qcom: Add sc8180x binding dt-bindings: pinctrl: qcom: Define common TLMM binding pinctrl: qcom: Add SM8350 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings pinctrl: samsung: use raw_spinlock for s3c64xx dt-bindings: mediatek: mt8192: Fix dt_binding_check warning pinctrl: qcom: spmi-mpp: Add PM8019 compatible pinctrl: pinmux: add function selector to pinmux-functions pinctrl: samsung: use raw_spinlock for locking pinctrl: clarify #pinctrl-cells for pinctrl-single,pins pinctrl: actions: Add the platform dependency to drivers ...
2021-02-15gpio: visconti: Add Toshiba Visconti GPIO supportNobuhiro Iwamatsu1-0/+23
Add the GPIO driver for Toshiba Visconti ARM SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2021-02-15pinctrl: mediatek: Fix trigger type setting follow for unexpected interruptHailong Fan1-2/+11
When flipping the polarity will be generated interrupt under certain circumstances, but GPIO external signal has not changed. Then, mask the interrupt before polarity setting, and clear the unexpected interrupt after trigger type setting completed. Remove mtk_eint_flip_edge: because mtk_eint_unmask already calls it. Signed-off-by: Hailong Fan <hailong.fan@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Link: https://lore.kernel.org/r/20210125041753.2214-1-hailong.fan@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: nuvoton: npcm7xx: Fix alignment of table header commentJonathan Neuschäfer1-1/+1
Make it so that each column label is in the column that it is supposed to refer to. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20210130162954.918803-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'"Claudiu Beznea1-53/+57
Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl warning. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea1-0/+27
SAMA7G5 supports slew rate configuration. Adapt the driver for this. For output switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: actions: Add depends on || COMPILE_TESTLinus Walleij1-3/+3
I happened to apply the v1 of the patch restriction the selection to ARM or ARM64, sorry for my sloppiness. Fixing up the mistake as I can't back the patch out now. Fixes: 5784921f7b6c ("pinctrl: actions: Add the platform dependency to drivers") Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: single: set function name when adding functionDrew Fustini1-0/+1
pcs_add_function() fails to set the function name in struct pcs_function when adding a new function. As a result this line in pcs_set_mux(): dev_dbg(pcs->dev, "enabling %s function%i\n", func->name, fselector); prints "(null)" for the function: pinctrl-single 44e10800.pinmux: enabling (null) function0 pinctrl-single 44e10800.pinmux: enabling (null) function1 pinctrl-single 44e10800.pinmux: enabling (null) function2 pinctrl-single 44e10800.pinmux: enabling (null) function3 With this fix, the output is now: pinctrl-single 44e10800.pinmux: enabling pinmux-uart0-pins function0 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function1 pinctrl-single 44e10800.pinmux: enabling pinmux-i2c0-pins function2 pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function3 Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Robert Nelson <robertcnelson@beagleboard.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210125203542.51513-1-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: qcom: Add sc8180x TLMM driverBjorn Andersson3-0/+1634
Add pinctrl driver for the sc8180x TLMM block. A noteworthy difference from previous TLMM blocks is that the registers for GPIO 177 through 189 are for some reason offset from the typical layout. Other than that the driver is same old... Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12pinctrl: qcom: Add SM8350 pinctrl driverVinod Koul3-0/+1659
This adds pincontrol driver for tlmm block found in SM8350 SoC This patch is based on initial code downstream by Raghavendra. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-27pinctrl: samsung: use raw_spinlock for s3c64xxChanho Park1-2/+2
Convert spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt for pinctrl-s3c64xx. Below patch converted spinlock_t to raw_spinlock_t but it didn't convert the s3c64xx's spinlock. Fixes: 1f306ecbe0f6 ("pinctrl: samsung: use raw_spinlock for locking") Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20210127001631.91209-1-chanho61.park@samsung.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-26pinctrl: qcom: spmi-mpp: Add PM8019 compatibleKonrad Dybcio1-0/+1
PM8019 provides 6 MPPs. Add a compatible to support them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210115171115.123155-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-26Merge tag 'intel-pinctrl-v5.12-1' of ↵Linus Walleij3-34/+88
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.12-1 * Enable pin control on Intel Alder Lake-P * Traverse through capabilities, convert them to features for the future use The following is an automated git shortlog grouped by driver: intel: - Convert capability list to features - Drop unnecessary check for predefined features - Split intel_pinctrl_add_padgroups() for better maintenance tigerlake: - Add Alder Lake-P ACPI ID
2021-01-24pinctrl: pinmux: add function selector to pinmux-functionsDrew Fustini1-1/+1
Add the function selector to the pinmux-functions debugfs output. This is an integer which is the index into the pinmux function tree. It will make it easier to correlate function name to function selector without having to count the lines in the output. Example output of "pinmux-functions": function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ] function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ] function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ] function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ] function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ] function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ] function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ] function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ] function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ] function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ] function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ] Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Robert Nelson <robertcnelson@beagleboard.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210123202212.528046-1-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-24pinctrl: samsung: use raw_spinlock for lockingChanho Park4-22/+22
This patch converts spin_[lock|unlock] functions of pin bank to raw_spinlock to support preempt-rt. This can avoid BUG() assertion when irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex which is preemptible when we apply preempt-rt patches. According to "Documentation/driver-api/gpio/driver.rst", "Realtime considerations: a realtime compliant GPIO driver should not use spinlock_t or any sleepable APIs (like PM runtime) as part of its irqchip implementation. - spinlock_t should be replaced with raw_spinlock_t.[1] " Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-22pinctrl: actions: Add the platform dependency to driversManivannan Sadhasivam1-0/+3
The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64 platforms. So let's add the correct platform dependency to avoid them being selected on the other. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210121062547.27173-1-manivannan.sadhasivam@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-22pinctrl: sunxi: Add support for the Allwinner H616-R pin controllerAndre Przywara3-0/+62
There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-22pinctrl: sunxi: Add support for the Allwinner H616 pin controllerAndre Przywara3-0/+554
Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: ingenic: Improve JZ4760 supportPaul Cercueil1-10/+28
- Add otg function and otg-vbus group. - Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special groups. Change the lcd-24bit group so that it only selects the pins that aren't in the lcd-18bit and lcd-generic groups (which breaks Device Tree in theory, but there is none out there for any JZ4760 based board, yet). Remove the lcd-no-pins group which is just useless. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove ste u300 driverArnd Bergmann3-1118/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove coh901 driverArnd Bergmann4-791/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove sirf atlas/prima driversArnd Bergmann8-9451/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21pinctrl: remove zte zx driverArnd Bergmann7-1590/+0
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: bcm: Simplify bool comparisonJiapeng Zhong1-1/+1
Fix the follow coccicheck warnings: ./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING: Comparison to bool. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com> Link: https://lore.kernel.org/r/1610705349-24310-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: ingenic: Only support SoCs enabled in configPaul Cercueil1-12/+48
Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves about 14 KiB, by allowing the compiler to garbage-collect all the functions and tables that correspond to SoCs that were disabled in the config. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18Merge tag 'renesas-pinctrl-for-v5.12-tag1' of ↵Linus Walleij6-17/+4531
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.12 - Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC.
2021-01-18pinctrl: qcom: Don't clear pending interrupts when enablingDouglas Anderson1-24/+50
In Linux, if a driver does disable_irq() and later does enable_irq() on its interrupt, I believe it's expecting these properties: * If an interrupt was pending when the driver disabled then it will still be pending after the driver re-enables. * If an edge-triggered interrupt comes in while an interrupt is disabled it should assert when the interrupt is re-enabled. If you think that the above sounds a lot like the disable_irq() and enable_irq() are supposed to be masking/unmasking the interrupt instead of disabling/enabling it then you've made an astute observation. Specifically when talking about interrupts, "mask" usually means to stop posting interrupts but keep tracking them and "disable" means to fully shut off interrupt detection. It's unfortunate that this is so confusing, but presumably this is all the way it is for historical reasons. Perhaps more confusing than the above is that, even though clients of IRQs themselves don't have a way to request mask/unmask vs. disable/enable calls, IRQ chips themselves can implement both. ...and yet more confusing is that if an IRQ chip implements disable/enable then they will be called when a client driver calls disable_irq() / enable_irq(). It does feel like some of the above could be cleared up. However, without any other core interrupt changes it should be clear that when an IRQ chip gets a request to "disable" an IRQ that it has to treat it like a mask of that IRQ. In any case, after that long interlude you can see that the "unmask and clear" can break things. Maulik tried to fix it so that we no longer did "unmask and clear" in commit 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback"), but it only handled the PDC case and it had problems (it caused sc7180-trogdor devices to fail to suspend). Let's fix. >From my understanding the source of the phantom interrupt in the were these two things: 1. One that could have been introduced in msm_gpio_irq_set_type() (only for the non-PDC case). 2. Edges could have been detected when a GPIO was muxed away. Fixing case #1 is easy. We can just add a clear in msm_gpio_irq_set_type(). Fixing case #2 is harder. Let's use a concrete example. In sc7180-trogdor.dtsi we configure the uart3 to have two pinctrl states, sleep and default, and mux between the two during runtime PM and system suspend (see geni_se_resources_{on,off}() for more details). The difference between the sleep and default state is that the RX pin is muxed to a GPIO during sleep and muxed to the UART otherwise. As per Qualcomm, when we mux the pin over to the UART function the PDC (or the non-PDC interrupt detection logic) is still watching it / latching edges. These edges don't cause interrupts because the current code masks the interrupt unless we're entering suspend. However, as soon as we enter suspend we unmask the interrupt and it's counted as a wakeup. Let's deal with the problem like this: * When we mux away, we'll mask our interrupt. This isn't necessary in the above case since the client already masked us, but it's a good idea in general. * When we mux back will clear any interrupts and unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Fixes: 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210114191601.v7.4.I7cf3019783720feb57b958c95c2b684940264cd1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmaskingDouglas Anderson1-4/+10
In commit 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") we tried to Ack interrupts during unmask. However, that patch forgot to check "intr_ack_high" so, presumably, it only worked for a certain subset of SoCs. Let's add a small accessor so we don't need to open-code the logic in both places. This was found by code inspection. I don't have any access to the hardware in question nor software that needs the Ack during unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.3.I32d0f4e174d45363b49ab611a13c3da8f1e87d0f@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: qcom: No need to read-modify-write the interrupt statusDouglas Anderson1-15/+8
When the Qualcomm pinctrl driver wants to Ack an interrupt, it does a read-modify-write on the interrupt status register. On some SoCs it makes sure that the status bit is 1 to "Ack" and on others it makes sure that the bit is 0 to "Ack". Presumably the first type of interrupt controller is a "write 1 to clear" type register and the second just let you directly set the interrupt status register. As far as I can tell from scanning structure definitions, the interrupt status bit is always in a register by itself. Thus with both types of interrupt controllers it is safe to "Ack" interrupts without doing a read-modify-write. We can do a simple write. It should be noted that if the interrupt status bit _was_ ever in a register with other things (like maybe status bits for other GPIOs): a) For "write 1 clear" type controllers then read-modify-write would be totally wrong because we'd accidentally end up clearing interrupts we weren't looking at. b) For "direct set" type controllers then read-modify-write would also be wrong because someone setting one of the other bits in the register might accidentally clear (or set) our interrupt. I say this simply to show that the current read-modify-write doesn't provide any sort of "future proofing" of the code. In fact (for "write 1 clear" controllers) the new code is slightly more "future proof" since it would allow more than one interrupt status bits to share a register. NOTE: this code fixes no bugs--it simply avoids an extra register read. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.2.I3635de080604e1feda770591c5563bd6e63dd39d@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0Douglas Anderson2-2/+3
There's currently a comment in the code saying function 0 is GPIO. Instead of hardcoding it, let's add a member where an SoC can specify it. No known SoCs use a number other than 0, but this just makes the code clearer. NOTE: no SoC code needs to be updated since we can rely on zero-initialization. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: sprd: Simplify bool comparisonYANG LI1-1/+1
Fix the following coccicheck warning: ./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to bool Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Link: https://lore.kernel.org/r/1610440080-68600-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18pinctrl: ti :iodelay: Fixed inconsistent indentingSouptick Joarder1-3/+2
Kernel test robot throws below warning -> smatch warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:708 ti_iodelay_pinconf_group_dbg_show() warn: inconsistent indenting Fixed the inconsistent indenting. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Link: https://lore.kernel.org/r/1610394585-4296-1-git-send-email-jrdr.linux@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-14pinctrl: renesas: r8a779a0: Add TPU pins, groups and functionsUlrich Hecht1-0/+44
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add TMU pins, groups and functionsUlrich Hecht1-0/+65
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functionsUlrich Hecht1-0/+72
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC driver. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add PWM pins, groups and functionsUlrich Hecht1-0/+77
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functionsUlrich Hecht1-0/+362
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add MMC pins, groups and functionsUlrich Hecht1-0/+79
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and functionUlrich Hecht1-0/+62
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functionsUlrich Hecht1-0/+134
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add DU pins, groups and functionUlrich Hecht1-0/+54
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functionsUlrich Hecht1-0/+137
This patch adds CANFD 0-7 and CANFD clock pinmux support for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functionsUlrich Hecht1-0/+595
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and PTP pins for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add I2C pins, groups and functionsUlrich Hecht1-0/+107
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functionsUlrich Hecht1-0/+156
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Initial R8A779A0 (V3U) PFC supportUlrich Hecht5-0/+2529
This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC, including bias, drive strength and voltage control. Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Add PORT_GP_CFG_{2,31} macrosUlrich Hecht1-4/+12
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Add I/O voltage level flagUlrich Hecht2-2/+23
This patch adds config macros describing the voltage levels available on a pin. The current default (3.3V/1.8V) maps to zero to avoid having to change existing PFC implementations. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14pinctrl: renesas: Implement unlock register masksUlrich Hecht2-11/+19
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12pinctrl: renesas: checker: Restrict checks to Renesas platformsGeert Uytterhoeven1-0/+4
When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin control driver runs sanity checks against the pin control tables. This may cause lots of output on the console, and can be annoying in ARM multi-platform kernels. Fix this by only running the checks when running on SuperH, or on a DT platform supported by the Renesas pin controller driver. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
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