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path: root/drivers/pinctrl
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2019-12-13pinctrl: lynxpoint: Implement ->pin_dbg_show()Andy Shevchenko1-0/+23
The introduced callback ->pin_dbg_show() is useful for debugging. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Add pin control operationsAndy Shevchenko1-1/+314
Add implementation for: - pin control, group information retrieval: count, name and pins - pin muxing: - function information (count, name and groups) - mux setting - GPIO control (enable, disable, set direction) - pin configuration: - pull disable, up and down - any other option is treated as not supported. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Reuse struct intel_pinctrl in the driverAndy Shevchenko1-24/+60
We may use now available struct intel_pinctrl in the driver. No functional change implied. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Add pin control data structuresAndy Shevchenko1-2/+124
In order to implement pin control for Intel Lynxpoint, we need data structures in which to store and pass along pin, community and SoC data information. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Implement intel_gpio_get_direction callbackAndy Shevchenko1-0/+11
Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Implement ->irq_ack() callbackAndy Shevchenko1-3/+14
Instead of playing tricks with registers in the interrupt handler, utilize the IRQ chip core for ACKing interrupts properly. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Move ownership check to IRQ chipAndy Shevchenko1-6/+6
There is nothing wrong with requesting pin that owned by ACPI. The only difference is how interrupt status will be reflected. It means that in ACPI mode we may not use pin as GPIO-backed IRQ. Taking above into consideration, move the check from GPIO to IRQ chip callback. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Move lp_irq_type() closer to IRQ related routinesAndy Shevchenko1-44/+44
Consolidate IRQ routines for better maintenance. While here, rename lp_irq_type() to lp_irq_set_type() to be in align with a callback name. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Move ->remove closer to ->probe()Andy Shevchenko1-6/+6
Consolidate ->remove and ->probe() callbacks for better maintenance. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Extract lp_gpio_acpi_use() for future useAndy Shevchenko1-2/+12
We may need this function for other features in the pin control driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Convert unsigned to unsigned intAndy Shevchenko1-12/+12
Simple type conversion with no functional change implied. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Switch to memory mapped IO accessorsAndy Shevchenko1-44/+44
Convert driver to use memory mapped IO accessors. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Keep pointer to struct device instead of its containerAndy Shevchenko1-7/+7
There is no need to keep pointer to struct platform_device, which is container of struct device, because the latter is what have been used everywhere outside of ->probe() path. In any case we may derive pointer to the container when needed. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Relax GPIO request rulesAndy Shevchenko1-3/+11
A pin in native mode still can be requested as GPIO, though we assume that firmware has configured it properly, which sometimes is not the case. Here we allow turning the pin as GPIO to avoid potential issues, but issue warning that something might be wrong. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Assume 2 bits for mode selectorAndy Shevchenko1-2/+4
New generations can use 2 bits for mode selector. Update the code to support it. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Use standard pattern for memory allocationAndy Shevchenko1-1/+1
The pattern foo = kmalloc(sizeof(*foo), GFP_KERNEL); has an advantage when foo type is changed. Since we are planning a such, better to be prepared by using standard pattern for memory allocation. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Use %pR to print IO resourceAndy Shevchenko1-2/+1
Replace explicit casting by pointer to struct resource with specifier replacement to %pR to print the IO resource. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Drop useless assignmentAndy Shevchenko1-1/+1
There is no need to assign ret variable in ->probe(). Drop useless assignment. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Correct amount of pinsAndy Shevchenko1-6/+6
When we count from 0 it's possible to get into off-by-one error. That's what had happened to this driver. So, correct amount of pins and related typos in the code. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Use raw_spinlock for lockingAndy Shevchenko1-14/+14
The Intel Lynxpoint pinctrl driver implements irqchip callbacks which are called with desc->lock raw_spinlock held. In mainline this is fine because spinlock resolves to raw_spinlock. However, running the same code in -rt we will get a BUG() asserted. This is because in -rt spinlocks are preemptible so taking the driver private spinlock in irqchip callbacks causes might_sleep() to trigger. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: lynxpoint: Move GPIO driver to pin controller folderAndy Shevchenko3-0/+482
Move Lynxpoint GPIO driver under Intel pin control umbrella for further transformation to a real pin control driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: baytrail: Reuse struct intel_pinctrl in the driverAndy Shevchenko1-99/+87
We may use now available struct intel_pinctrl in the driver. No functional change implied. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: baytrail: Use local variable to keep device pointerAndy Shevchenko1-9/+10
Use local variable to keep device pointer in order to increase readability of the driver. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: baytrail: Keep pointer to struct device instead of its containerAndy Shevchenko1-29/+29
There is no need to keep pointer to struct platform_device, which is container of struct device, because the latter is what have been used everywhere outside of ->probe() path. In any case we may derive pointer to the container when needed. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: intel: Share struct intel_pinctrl for wider useAndy Shevchenko2-34/+45
There are few drivers for Intel SoC GPIO which may utilize the same data structure to describe this IP. Share struct intel_pinctrl for wider user. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: intel: Use GPIO direction definitionsMatti Vaittinen1-1/+4
Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: cherryview: Use GPIO direction definitionsMatti Vaittinen1-1/+4
Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-13pinctrl: baytrail: Use GPIO direction definitionsMatti Vaittinen1-2/+2
Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: baytrail: Move IRQ valid mask initialization to a dedicated callbackAndy Shevchenko1-14/+9
There is a logical continuation of the commit 5fbe5b5883f8 ("gpio: Initialize the irqchip valid_mask with a callback") to split IRQ initialization to hardware and valid mask setup parts. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: sh-pfc: Remove use of ARCH_R8A7796Geert Uytterhoeven1-1/+1
CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit 39e57e14d7eaf818 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191211100308.6958-1-geert+renesas@glider.be
2019-12-13pinctrl: core: Add pinctrl_select_default_state() and export itUlf Hansson1-14/+19
It has turned out that some mmc host drivers, but perhaps also others drivers, needs to reset the pinctrl into the default state (PINCTRL_STATE_DEFAULT). However, they can't use the existing pinctrl_pm_select_default_state(), as that requires CONFIG_PM to be set. This leads to open coding, as they need to look up the default state themselves and then select it. To avoid the open coding, let's introduce pinctrl_select_default_state() and make it available independently of CONFIG_PM. As a matter of fact, this makes it more consistent with the behaviour of the driver core, as it already tries to looks up the default state during probe. Going forward, users of pinctrl_pm_select_default_state() are encouraged to move to pinctrl_select_default_state(), so the old API can be removed. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191206170821.29711-2-ulf.hansson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: Modify Kconfig to fix linker errorRahul Tanwar1-0/+1
Fix below linker error ld: drivers/pinctrl/pinctrl-equilibrium.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-equilibrium.c:(.text+0xb): undefined reference to `pinconf_generic_dt_node_to_map' Caused by below commit 1948d5c51dba ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") by adding 'depends on OF' in Kconfig driver entry. Reported-by: Randy Dunlap <rdunlap@infradead.org>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/ba937f271d1a2173828a2325990d62cb36d61595.1575514110.git.rahul.tanwar@linux.intel.com Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13Merge tag 'intel-pinctrl-v5.5-2' of ↵Linus Walleij2-134/+173
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.5-2 * Fix Baytrail silicon issue by using a global lock * Fix North community pin names that user will assume their functions * Convert Cherryview and Baytrail to pass IRQ chip along with GPIO one The following is an automated git shortlog grouped by driver: baytrail: - Pass irqchip when adding gpiochip - Add GPIO <-> pin mapping ranges via callback - Update North Community pin list - Really serialize all register accesses cherryview: - Pass irqchip when adding gpiochip - Add GPIO <-> pin mapping ranges via callback - Split out irq hw-init into a separate helper function
2019-12-13pinctrl: pinmux: fix a possible null pointer in pinmux_can_be_used_for_gpioAlexandre Torgue1-1/+1
This commit adds a check on ops pointer to avoid a kernel panic when ops->strict is used. Indeed, on some pinctrl driver (at least for pinctrl-stmfx) the pinmux ops is not implemented. Let's assume than gpio can be used in this case. Fixes: 472a61e777fe ("pinctrl/gpio: Take MUX usage into account") Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Link: https://lore.kernel.org/r/20191204144106.10876-1-alexandre.torgue@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed-g6: Add AST2600 pinconf supportJohnny Huang2-0/+297
The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed: Use masks to describe pinconf bitfieldsJohnny Huang4-19/+20
Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed: Move aspeed_pin_config_map to separate source fileJohnny Huang4-33/+44
The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed: Add ASPEED_SB_PINCONF() helperJohnny Huang3-181/+188
This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed-g6: Add support for the AST2600 USB pinmuxJohnny Huang2-1/+69
AST2600 has two USB ports, A, B: Port A supports 4 distinct modes: 1. PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-4-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-13pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux configJohnny Huang1-1/+29
These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-3-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-12pinctrl: aspeed-g6: Fix LPC/eSPI mux configurationAndrew Jeffery1-16/+8
Early revisions of the AST2600 datasheet are conflicted about the state of the LPC/eSPI strapping bit (SCU510[6]). Conversations with ASPEED determined that the reference pinmux configuration tables were in error and the SCU documentation contained the correct configuration. Update the driver to reflect the state described in the SCU documentation. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202050110.15340-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-12pinctrl: stm32: Use the correct style for SPDX License IdentifierNishad Kamdar1-1/+1
This patch corrects the SPDX License Identifier style in header file related to STMicroelectronics pinctrl driver. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Link: https://lore.kernel.org/r/14bb695da50f7af8499e7dfc32c2ab753d92a3e9.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-12pinctrl: meson-axg: Use the correct style for SPDX License IdentifierNishad Kamdar1-1/+1
This patch corrects the SPDX License Identifier style in header file related Meson axg SoC pinctrl driver. It assigns explicit block comment for the SPDX License Identifier. Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Link: https://lore.kernel.org/r/bcb86aa22d8d8499502bbd8c54a364be24886a86.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-12pinctrl: mediatek: Use the correct style for SPDX License IdentifierNishad Kamdar1-1/+1
This patch corrects the SPDX License Identifier style in header file related mediatek mt2712 pinctrl driver. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used). Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Link: https://lore.kernel.org/r/2994fb2f3375790e832396cdbb0a279dc8c8839f.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-11pinctrl: samsung: Clarify the option titles/namesKrzysztof Kozlowski1-3/+3
The config options toggle Samsung Exynos SoCs pinctrl drivers, not the driver data. Clarify this in the option title/name and also make it consistent with other Samsung entries. No functional change. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-11pinctrl: samsung: Enable compile test for build coverageKrzysztof Kozlowski1-3/+5
The Samsung pinctrl drivers require only GPIOLIB and OF for building. The drivers should be buildable on all architectures so enable COMPILE_TEST. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-09pinctrl: baytrail: Group GPIO IRQ chip initializationAndy Shevchenko1-1/+1
After commit 5ea422750a9f ("pinctrl: baytrail: Pass irqchip when adding gpiochip") the GPIO IRQ chip structure is being initialized under conditional when IRQ resource has been discovered. But that commit left aside the assignment of ->init_valid_mask() callback that is done unconditionally. For sake of consistency and preventing some garbage in GPIO IRQ chip structure group initialization together. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-09pinctrl: baytrail: Allocate IRQ chip dynamicAndy Shevchenko1-10/+9
Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: 9f573b98ca50 ("pinctrl: baytrail: Update irq chip operations") Depends-on: ca8a958e2acb ("pinctrl: baytrail: Pass irqchip when adding gpiochip") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-09pinctrl: cherryview: Pass irqchip when adding gpiochipHans de Goede1-23/+22
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-09pinctrl: cherryview: Add GPIO <-> pin mapping ranges via callbackHans de Goede1-11/+22
When IRQ chip is instantiated via GPIO library flow, the few functions, in particular the ACPI event registration mechanism, on some of ACPI based platforms expect that the pin ranges are initialized to that point. Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 06:14:32 +0300