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2024-03-05pinctrl: starfive: jh7110: Unset .strict in pinmux_opsHal Feng1-1/+0
Allow simultaneous use of the same pin for GPIO and another function. This feature is used in HDMI hot plug detect. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-02-05pinctrl: baytrail: Fix types of config value in byt_pin_config_set()Andy Shevchenko1-1/+2
[ Upstream commit 1a856a22e6036c5f0d6da7568b4550270f989038 ] When unpacked, the config value is split to two of different types. Fix the types accordingly. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: cy8c95x0: Fix get_pincfgPatrick Rudolph1-0/+2
[ Upstream commit 94c71705cc49092cef60ece13a28680809096fd4 ] Invert the register value for PIN_CONFIG_OUTPUT_ENABLE to return the opposite of PIN_CONFIG_INPUT_ENABLE. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-3-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: cy8c95x0: Fix regressionPatrick Rudolph1-0/+10
[ Upstream commit 04dfca968cf7349773126340991b68a83378aca2 ] Commit 1fa3df901f2c ("pinctrl: cy8c95x0: Remove custom ->set_config()") removed support for PIN_CONFIG_INPUT_ENABLE and PIN_CONFIG_OUTPUT. Add the following options to restore functionality: - PIN_CONFIG_INPUT_ENABLE - PIN_CONFIG_OUTPUT_ENABLE Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: cy8c95x0: Fix typoPatrick Rudolph1-1/+1
[ Upstream commit 47b1fa48116238208c1b1198dba10f56fc1b6eb2 ] Fix typo to make pinctrl-cy8c95x compile again. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: amd: Mask non-wake source pins with interrupt enabled at suspendMario Limonciello2-0/+14
[ Upstream commit 2fff0b5e1a6b9c577b4dd4958902c877159c856b ] If a pin isn't marked as a wake source processing any interrupts is just going to destroy battery life. The APU may wake up from a hardware sleep state to process the interrupt but not return control to the OS. Mask interrupt for all non-wake source pins at suspend. They'll be re-enabled at resume. Reported-and-tested-by: Marcus Aram <marcus+oss@oxar.nl> Reported-and-tested-by: Mark Herbert <mark.herbert42@gmail.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2812 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20231203032431.30277-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: lochnagar: Don't build on MIPSCharles Keepax1-1/+2
[ Upstream commit 6588732445ff19f6183f0fa72ddedf67e5a5be32 ] MIPS appears to define a RST symbol at a high level, which clashes with some register naming in the driver. Since there is currently no case for running this driver on MIPS devices simply cut off the build of this driver on MIPS. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311071303.JJMAOjy4-lkp@intel.com/ Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20231115162853.1891940-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-20pinctrl: s32cc: Avoid possible string truncationChester Lin1-2/+2
[ Upstream commit 08e8734d877a9a0fb8af1254a4ce58734fbef296 ] With "W=1" and "-Wformat-truncation" build options, the kernel test robot found a possible string truncation warning in pinctrl-s32cc.c, which uses an 8-byte char array to hold a memory region name "map%u". Since the maximum number of digits that a u32 value can present is 10, and the "map" string occupies 3 bytes with a termination '\0', which means the rest 4 bytes cannot fully present the integer "X" that exceeds 4 digits. Here we check if the number >= 10000, which is the lowest value that contains more than 4 digits. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311030159.iyUGjNGF-lkp@intel.com/ Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20231107141044.24058-1-clin@suse.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-01-01pinctrl: starfive: jh7100: ignore disabled device tree nodesNam Cao1-2/+2
commit 5c584f175d32f9cc66c909f851cd905da58b39ea upstream. The driver always registers pin configurations in device tree. This can cause some inconvenience to users, as pin configurations in the base device tree cannot be disabled in the device tree overlay, even when the relevant devices are not used. Ignore disabled pin configuration nodes in device tree. Fixes: ec648f6b7686 ("pinctrl: starfive: Add pinctrl driver for StarFive SoCs") Cc: <stable@vger.kernel.org> Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/fe4c15dcc3074412326b8dc296b0cbccf79c49bf.1701422582.git.namcao@linutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-01-01pinctrl: starfive: jh7110: ignore disabled device tree nodesNam Cao1-2/+2
commit f6e3b40a2c89c1d832ed9cb031dc9825bbf43b7c upstream. The driver always registers pin configurations in device tree. This can cause some inconvenience to users, as pin configurations in the base device tree cannot be disabled in the device tree overlay, even when the relevant devices are not used. Ignore disabled pin configuration nodes in device tree. Fixes: 447976ab62c5 ("pinctrl: starfive: Add StarFive JH7110 sys controller driver") Cc: <stable@vger.kernel.org> Signed-off-by: Nam Cao <namcao@linutronix.de> Link: https://lore.kernel.org/r/fd8bf044799ae50a6291ae150ef87b4f1923cacb.1701422582.git.namcao@linutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-01-01pinctrl: at91-pio4: use dedicated lock class for IRQAlexis Lothoré1-0/+8
[ Upstream commit 14694179e561b5f2f7e56a0f590e2cb49a9cc7ab ] Trying to suspend to RAM on SAMA5D27 EVK leads to the following lockdep warning: ============================================ WARNING: possible recursive locking detected 6.7.0-rc5-wt+ #532 Not tainted -------------------------------------------- sh/92 is trying to acquire lock: c3cf306c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 but task is already holding lock: c3d7c46c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 6 locks held by sh/92: #0: c3aa0258 (sb_writers#6){.+.+}-{0:0}, at: ksys_write+0xd8/0x178 #1: c4c2df44 (&of->mutex){+.+.}-{3:3}, at: kernfs_fop_write_iter+0x138/0x284 #2: c32684a0 (kn->active){.+.+}-{0:0}, at: kernfs_fop_write_iter+0x148/0x284 #3: c232b6d4 (system_transition_mutex){+.+.}-{3:3}, at: pm_suspend+0x13c/0x4e8 #4: c387b088 (&dev->mutex){....}-{3:3}, at: __device_suspend+0x1e8/0x91c #5: c3d7c46c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 stack backtrace: CPU: 0 PID: 92 Comm: sh Not tainted 6.7.0-rc5-wt+ #532 Hardware name: Atmel SAMA5 unwind_backtrace from show_stack+0x18/0x1c show_stack from dump_stack_lvl+0x34/0x48 dump_stack_lvl from __lock_acquire+0x19ec/0x3a0c __lock_acquire from lock_acquire.part.0+0x124/0x2d0 lock_acquire.part.0 from _raw_spin_lock_irqsave+0x5c/0x78 _raw_spin_lock_irqsave from __irq_get_desc_lock+0xe8/0x100 __irq_get_desc_lock from irq_set_irq_wake+0xa8/0x204 irq_set_irq_wake from atmel_gpio_irq_set_wake+0x58/0xb4 atmel_gpio_irq_set_wake from irq_set_irq_wake+0x100/0x204 irq_set_irq_wake from gpio_keys_suspend+0xec/0x2b8 gpio_keys_suspend from dpm_run_callback+0xe4/0x248 dpm_run_callback from __device_suspend+0x234/0x91c __device_suspend from dpm_suspend+0x224/0x43c dpm_suspend from dpm_suspend_start+0x9c/0xa8 dpm_suspend_start from suspend_devices_and_enter+0x1e0/0xa84 suspend_devices_and_enter from pm_suspend+0x460/0x4e8 pm_suspend from state_store+0x78/0xe4 state_store from kernfs_fop_write_iter+0x1a0/0x284 kernfs_fop_write_iter from vfs_write+0x38c/0x6f4 vfs_write from ksys_write+0xd8/0x178 ksys_write from ret_fast_syscall+0x0/0x1c Exception stack(0xc52b3fa8 to 0xc52b3ff0) 3fa0: 00000004 005a0ae8 00000001 005a0ae8 00000004 00000001 3fc0: 00000004 005a0ae8 00000001 00000004 00000004 b6c616c0 00000020 0059d190 3fe0: 00000004 b6c61678 aec5a041 aebf1a26 This warning is raised because pinctrl-at91-pio4 uses chained IRQ. Whenever a wake up source configures an IRQ through irq_set_irq_wake, it will lock the corresponding IRQ desc, and then call irq_set_irq_wake on "parent" IRQ which will do the same on its own IRQ desc, but since those two locks share the same class, lockdep reports this as an issue. Fix lockdep false positive by setting a different class for parent and children IRQ Fixes: 776180848b57 ("pinctrl: introduce driver for Atmel PIO4 controller") Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> Link: https://lore.kernel.org/r/20231215-lockdep_warning-v1-1-8137b2510ed5@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-12-08pinctrl: stm32: fix array read out of boundAntonio Borneo1-3/+5
[ Upstream commit edd48fd9d45370d6c8ba0dd834fcc51ff688cc87 ] The existing code does not verify if the "tentative" index exceeds the size of the array, causing out of bound read. Issue identified with kasan. Check the index before using it. Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Fixes: 32c170ff15b0 ("pinctrl: stm32: set default gpio line names using pin names") Link: https://lore.kernel.org/r/20231107110520.4449-1-antonio.borneo@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-12-08pinctrl: stm32: Add check for devm_kcallocChen Ni1-0/+5
[ Upstream commit b0eeba527e704d6023a6cd9103f929226e326b03 ] Add check for the return value of devm_kcalloc() and return the error if it fails in order to avoid NULL pointer dereference. Fixes: 32c170ff15b0 ("pinctrl: stm32: set default gpio line names using pin names") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Acked-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20231031080807.3600656-1-nichen@iscas.ac.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-12-08pinctrl: avoid reload of p state in list iterationMaria Yu1-3/+3
commit 4198a9b571065978632276264e01d71d68000ac5 upstream. When in the list_for_each_entry iteration, reload of p->state->settings with a local setting from old_state will turn the list iteration into an infinite loop. The typical symptom when the issue happens, will be a printk message like: "not freeing pin xx (xxx) as part of deactivating group xxx - it is already used for some other setting". This is a compiler-dependent problem, one instance occurred using Clang version 10.0 on the arm64 architecture with linux version 4.19. Fixes: 6e5e959dde0d ("pinctrl: API changes to support multiple states per device") Signed-off-by: Maria Yu <quic_aiquny@quicinc.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20231115102824.23727-1-quic_aiquny@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-11-20pinctrl: renesas: rzg2l: Make reverse order of enable() for disable()Biju Das1-1/+2
[ Upstream commit dd462cf53e4dff0f4eba5e6650e31ceddec74c6f ] We usually do reverse order of enable() for disable(). Currently, the ordering of irq_chip_disable_parent() is not correct in rzg2l_gpio_irq_disable(). Fix the incorrect order. Fixes: db2e5f21a48e ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230918123355.262115-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-11-20pinctrl: baytrail: fix debounce disable caseRaag Jadav1-2/+9
[ Upstream commit 2d325e54d9e2e4ae247c9fd03f810208ce958c51 ] We don't need to update debounce pulse value in case debounce is to be disabled. Break such a case where arg value is zero. Fixes: 4cfff5b7af8b ("pinctrl: baytrail: consolidate common mask operation") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/linux-gpio/d164d471-5432-4c3c-afdb-33dc8f53d043@moroto.mountain/ Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-10-19Revert "pinctrl: avoid unsafe code pattern in find_pinctrl()"Andy Shevchenko1-9/+7
The commit breaks MMC enumeration on the Intel Merrifield plaform. Before: [ 36.439057] mmc0: SDHCI controller on PCI [0000:00:01.0] using ADMA [ 36.450924] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA [ 36.459355] mmc1: SDHCI controller on PCI [0000:00:01.2] using ADMA [ 36.706399] mmc0: new DDR MMC card at address 0001 [ 37.058972] mmc2: new ultra high speed DDR50 SDIO card at address 0001 [ 37.278977] mmcblk0: mmc0:0001 H4G1d 3.64 GiB [ 37.297300] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 After: [ 36.436704] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA [ 36.436720] mmc1: SDHCI controller on PCI [0000:00:01.0] using ADMA [ 36.463685] mmc0: SDHCI controller on PCI [0000:00:01.2] using ADMA [ 36.720627] mmc1: new DDR MMC card at address 0001 [ 37.068181] mmc2: new ultra high speed DDR50 SDIO card at address 0001 [ 37.279998] mmcblk1: mmc1:0001 H4G1d 3.64 GiB [ 37.302670] mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 This reverts commit c153a4edff6ab01370fcac8e46f9c89cca1060c2. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231017141806.535191-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-16pinctrl: qcom: lpass-lpi: fix concurrent register updatesKrzysztof Kozlowski1-6/+11
The Qualcomm LPASS LPI pin controller driver uses one lock for guarding Read-Modify-Write code for slew rate registers. However the pin configuration and muxing registers have exactly the same RMW code but are not protected. Pin controller framework does not provide locking here, thus it is possible to trigger simultaneous change of pin configuration registers resulting in non-atomic changes. Protect from concurrent access by re-using the same lock used to cover the slew rate register. Using the same lock instead of adding second one will make more sense, once we add support for newer Qualcomm SoC, where slew rate is configured in the same register as pin configuration/muxing. Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-12pinctrl: renesas: rzn1: Enable missing PINMUXRalph Siemsen1-0/+1
Enable pin muxing (eg. programmable function), so that the RZ/N1 GPIO pins will be configured as specified by the pinmux in the DTS. This used to be enabled implicitly via CONFIG_GENERIC_PINMUX_FUNCTIONS, however that was removed, since the RZ/N1 driver does not call any of the generic pinmux functions. Fixes: 1308fb4e4eae14e6 ("pinctrl: rzn1: Do not select GENERIC_PIN{CTRL_GROUPS,MUX_FUNCTIONS}") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231004200008.1306798-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-27Revert "pinctrl: tegra: Add support to display pin function"Linus Walleij2-19/+2
This reverts commit d1cd5b51bc9152dc2b63c5f843590272d6694d50. It was reported that some I2C3 functions stop working after this patch, and it is just debug help so let's revert it and investigate. Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-25pinctrl: avoid unsafe code pattern in find_pinctrl()Dmitry Torokhov1-7/+9
The code in find_pinctrl() takes a mutex and traverses a list of pinctrl structures. Later the caller bumps up reference count on the found structure. Such pattern is not safe as pinctrl that was found may get deleted before the caller gets around to increasing the reference count. Fix this by taking the reference count in find_pinctrl(), while it still holds the mutex. Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Link: https://lore.kernel.org/r/ZQs1RgTKg6VJqmPs@google.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12pinctrl: starfive: jh7110: Add system pm ops to save and restore contextHal Feng4-0/+52
Add system pm ops to save and restore pinctrl registers when suspending and resuming the driver, respectively. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230905122105.117000-3-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12pinctrl: starfive: jh7110: Fix failure to set irq after CONFIG_PM is enabledHal Feng1-2/+0
The issue was found when we enabled CONFIG_PM and tested edge events using libgpiod. > # gpiomon -r gpiochip0 55 > gpiomon: error waiting for events: Permission denied `gpiomon` will call irq_chip_pm_get() and then call pm_runtime_resume_and_get() if (IS_ENABLED(CONFIG_PM) && sfp->gc.irq.domain->pm_dev). pm_runtime_resume_and_get() will fail if the runtime pm of pinctrl device is disabled. As we expect the pinctrl driver can be always working and never suspend during runtime, unset sfp->gc.irq.domain->pm_dev to make sure pm_runtime_resume_and_get() won't be called when setting irq. Fixes: 447976ab62c5 ("pinctrl: starfive: Add StarFive JH7110 sys controller driver") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230905122105.117000-2-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12pinctrl: nuvoton: wpcm450: fix out of bounds writeMikhail Kobuk1-3/+3
Write into 'pctrl->gpio_bank' happens before the check for GPIO index validity, so out of bounds write may happen. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: a1d1e0e3d80a ("pinctrl: nuvoton: Add driver for WPCM450") Signed-off-by: Mikhail Kobuk <m.kobuk@ispras.ru> Reviewed-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20230825101532.6624-1-m.kobuk@ispras.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-11pinctrl: lantiq: Remove unsued declaration ltq_pinctrl_unregister()YueHaibing1-1/+0
Commit 3f8c50c9b110 ("OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support") declared but never implemented it, so can be removed. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230825092706.14680-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-31Merge tag 'pinctrl-v6.6-1' of ↵Linus Torvalds167-3242/+2646
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have some patches to DTS[I] files in arm and arm64 as well, that were merged here as DT headers were being changed. The most interesting stuff is the Intel Tangier chip support and AMLogic C3 in my opinion. No core changes this time. Drivers: - Intel Tangier SoC pin control support - AMLogic C3 SoC pin control support - Texas Instruments AM654 SoC pin control support - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin control support - Qualcomm PMX75 and PM7550BA (Power Management) pin control support - Qualcomm PMC8180 and PMC8180C (Power Management) pin control support - DROP the Oxnas driver as there is not enough of community interest to keep carrying this ARM(11) port Enhancements: - Bias control in the MT7986 pin control driver - Misc device tree binding enhancements such as the Broadcom 11351 being converted to YAML - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use - Clean up some SPDX headers - Handle non-unique devicetree subnode names in two Renesas drivers" * tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl: mlxbf3: Remove gpio_disable_free() pinctrl: use capital "OR" for multiple licenses in SPDX dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes pinctrl: cherryview: fix address_space_handler() argument pinctrl: intel: consolidate ACPI dependency pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: mediatek: assign functions to configure pin bias on MT7986 pinctrl: mediatek: fix pull_type data for MT7981 dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties dt-bindings: pinctrl: Drop 'phandle' properties pinctrl: lynxpoint: Make use of pm_ptr() pinctrl: baytrail: Make use of pm_ptr() pinctrl: intel: Switch to use exported namespace pinctrl: lynxpoint: reuse common functions from pinctrl-intel pinctrl: cherryview: reuse common functions from pinctrl-intel ...
2023-08-29Merge tag 'spi-v6.6' of ↵Linus Torvalds3-0/+622
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "There's been quite a lot of generic activity here, but more administrative than featuers. We also have a bunch of new drivers, including one that's part of a MFD so we pulled in the core parts of that: - Lots of work from both Yang Yingliang and Andy Shevchenko on moving to host/device/controller based terminology for devices. - QuadSPI SPI support for Allwinner sun6i. - New device support Cirrus Logic CS43L43, Longsoon, Qualcomm GENI QuPv3 and StarFive JH7110 QSPI" * tag 'spi-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (151 commits) spi: at91-usart: Use PTR_ERR_OR_ZERO() to simplify code spi: spi-sn-f-ospi: switch to use modern name spi: sifive: switch to use modern name spi: sh: switch to use modern name spi: sh-sci: switch to use modern name spi: sh-msiof: switch to use modern name spi: sh-hspi: switch to use modern name spi: sc18is602: switch to use modern name spi: s3c64xx: switch to use modern name spi: rzv2m-csi: switch to use devm_spi_alloc_host() spi: rspi: switch to use spi_alloc_host() spi: rockchip: switch to use modern name spi: rockchip-sfc: switch to use modern name spi: realtek-rtl: switch to use devm_spi_alloc_host() spi: rb4xx: switch to use modern name spi: qup: switch to use modern name spi: spi-qcom-qspi: switch to use modern name spi: pxa2xx: switch to use modern name spi: ppc4xx: switch to use modern name spi: spl022: switch to use modern name ...
2023-08-25Merge tag 'intel-pinctrl-v6.6-1' of ↵Linus Walleij32-1613/+896
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.6-1 * New library driver for Intel MID to deduplicate code (Raag Jadav) * Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav) * Move most of the exported functions to the PINCTRL_INTEL namespace * Make use of pm_ptr() in Bay Trail and Lynxpoint drivers * Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers * Consolidata ACPI dependency in Kconfig (Raag Jadav) * Fix address_space_handler() argument in Cherryview driver (Raag Jadav) * Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav) The following is an automated git shortlog grouped by driver: at91: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper baytrail: - Make use of pm_ptr() - reuse common functions from pinctrl-intel - consolidate common mask operation cherryview: - fix address_space_handler() argument - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper - reuse common functions from pinctrl-intel intel: - consolidate ACPI dependency - Switch to use exported namespace - export common pinctrl functions lynxpoint: - Make use of pm_ptr() - reuse common functions from pinctrl-intel Merge patch series: - Merge patch series "Introduce Intel Tangier pinctrl driver" - Merge patch series "Reuse common functions from pinctrl-intel" merrifield: - Adapt to Intel Tangier driver moorefield: - Adapt to Intel Tangier driver mvebu: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: - Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper renesas: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper tangier: - Introduce Intel Tangier driver tegra: - Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-25pinctrl: mlxbf3: Remove gpio_disable_free()Asmaa Mnebhi1-14/+0
Remove support for gpio_disable_free() because it is called when the libgpiod command "gpioset" is invoked. This gives the GPIO control back to hardware which cancels out the effort to set the GPIO value. Reminder of the code flow to change a GPIO value from software: 1) All GPIOs are controlled by hardware by default 2) To change the GPIO value, enable software control via a mux. 3) Once software has control over the GPIO pin, the gpio-mlxbf3 driver will be able to change the direction and value of the GPIO. When the user runs "gpioset gpiochip0 0=0" for example, the gpio pin value should change from 1 to 0. In this case, mlxbf3_gpio_request_enable() is called via gpiochip_generic_request(). The latter switches GPIO control from hardware to software. Then the GPIO value is changed from 1 to 0. However, gpio_disable_free() is also called which changes control back to hardware which changes the GPIO value back to 1. Fixes: d11f932808dc ("pinctrl: mlxbf3: Add pinctrl driver support") Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230818164314.8505-2-asmaa@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-23pinctrl: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski5-7/+5
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Correct also the placement of SPDX identifier in pinctrl-meson-axg files: WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823085546.116494-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-22pinctrl: cherryview: fix address_space_handler() argumentRaag Jadav1-3/+2
First argument of acpi_*_address_space_handler() APIs is acpi_handle of the device, which is incorrectly passed in driver ->remove() path here. Fix it by passing the appropriate argument and while at it, make both API calls consistent using ACPI_HANDLE(). Fixes: a0b028597d59 ("pinctrl: cherryview: Add support for GMMR GPIO opregion") Cc: stable@vger.kernel.org Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-22pinctrl: intel: consolidate ACPI dependencyRaag Jadav1-19/+1
Since all the Intel specific platform drivers depend on ACPI, we can consolidate their config dependency. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko2-5/+2
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that, make sure the PM ops are used only in CONFIG_PM_SLEEP=y case by wrapping them in pm_sleep_ptr() macro. Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230717172821.62827-11-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko1-9/+7
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230717172821.62827-10-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko1-11/+3
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20230717172821.62827-9-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko1-6/+4
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. With that switch pm_ptr() to pm_sleep_ptr() as the above mentioned callbacks are only used for system sleep. The use of the pm_sleep_ptr() macro allows the compiler to always see the dev_pm_ops structure and related functions, while still allowing the unused code to be removed, without the need for the __maybe_unused markings. Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230717172821.62827-7-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko1-7/+3
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230717172821.62827-4-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: mediatek: assign functions to configure pin bias on MT7986Daniel Golle1-0/+8
Assign bias_disable_get/set and bias_get/set functions to allow configuring pin bias on MT7986. Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21pinctrl: mediatek: fix pull_type data for MT7981Daniel Golle1-31/+13
MediaTek has released pull_type data for MT7981 in their SDK. Use it and set functions to configure pin bias. Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21pinctrl: amd: Mask wake bits on probe againMario Limonciello1-0/+30
Shubhra reports that their laptop is heating up over s2idle. Even though it's getting into the deepest state, it appears to be having spurious wakeup events. While debugging a tangential issue with the RTC Carsten reports that recent 6.1.y based kernel face a similar problem. Looking at acpidump and GPIO register comparisons these spurious wakeup events are from the GPIO associated with the I2C touchpad on both laptops and occur even when the touchpad is not marked as a wake source by the kernel. This means that the boot firmware has programmed these bits and because Linux didn't touch them lead to spurious wakeup events from that GPIO. To fix this issue, restore most of the code that previously would clear all the bits associated with wakeup sources. This will allow the kernel to only program the wake up sources that are necessary. This is similar to what was done previously; but only the wake bits are cleared by default instead of interrupts and wake bits. If any other problems are reported then it may make sense to clear interrupts again too. Cc: Sachi King <nakato@nakato.io> Cc: stable@vger.kernel.org Cc: Thorsten Leemhuis <regressions@leemhuis.info> Fixes: 65f6c7c91cb2 ("pinctrl: amd: Revert "pinctrl: amd: disable and mask interrupts on probe"") Reported-by: Shubhra Prakash Nandi <email2shubhra@gmail.com> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217754 Reported-by: Carsten Hatger <xmb8dsv4@gmail.com> Link: https://bugzilla.kernel.org/show_bug.cgi?id=217626#c28 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230818144850.1439-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21Merge tag 'renesas-pinctrl-fixes-for-v6.5-tag2' of ↵Linus Walleij3-7/+38
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into fixes pinctrl: renesas: Fixes for v6.5 (take two) - Fix race conditions in pinctrl group and function creation/remove calls on the RZ/G2L, RZ/V2M, and RZ/A2 SoC families. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-18pinctrl: lynxpoint: Make use of pm_ptr()Andy Shevchenko1-4/+3
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. The lp_gpio_resume() is also assigned to .thaw and .restore members. This is not a problem as the function it enables input pins that had been disabled by firmware and repetion of that doesn't change the pin configuration, i.e. it is idempotent. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20230717172821.62827-6-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18mfd: Immutable branch between MFD, Pinctrl and soundwire due for the v6.6 ↵Mark Brown3-0/+622
merge window Merge tag 'ib-mfd-pinctrl-soundwire-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into tmp Immutable branch between MFD, Pinctrl and soundwire due for the v6.6 merge window
2023-08-18pinctrl: baytrail: Make use of pm_ptr()Andy Shevchenko1-8/+3
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20230717172821.62827-3-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18pinctrl: renesas: rza2: Add lock around ↵Biju Das1-2/+15
pinctrl_generic{{add,remove}_group,{add,remove}_function} The pinctrl group and function creation/remove calls expect caller to take care of locking. Add lock around these functions. Fixes: b59d0e782706 ("pinctrl: Add RZ/A2 pin and gpio controller") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230815131558.33787-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-18pinctrl: renesas: rzv2m: Fix NULL pointer dereference in ↵Biju Das1-2/+11
rzv2m_dt_subnode_to_map() Fix the below random NULL pointer crash during boot by serializing pinctrl group and function creation/remove calls in rzv2m_dt_subnode_to_map() with mutex lock. Crash logs: pc : __pi_strcmp+0x20/0x140 lr : pinmux_func_name_to_selector+0x68/0xa4 Call trace: __pi_strcmp+0x20/0x140 pinmux_generic_add_function+0x34/0xcc rzv2m_dt_subnode_to_map+0x2e4/0x418 rzv2m_dt_node_to_map+0x15c/0x18c pinctrl_dt_to_map+0x218/0x37c create_pinctrl+0x70/0x3d8 While at it, add a comment for lock. Fixes: 92a9b8252576 ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230815131558.33787-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-18pinctrl: renesas: rzg2l: Fix NULL pointer dereference in ↵Biju Das1-3/+12
rzg2l_dt_subnode_to_map() Fix the below random NULL pointer crash during boot by serializing pinctrl group and function creation/remove calls in rzg2l_dt_subnode_to_map() with mutex lock. Crash log: pc : __pi_strcmp+0x20/0x140 lr : pinmux_func_name_to_selector+0x68/0xa4 Call trace: __pi_strcmp+0x20/0x140 pinmux_generic_add_function+0x34/0xcc rzg2l_dt_subnode_to_map+0x314/0x44c rzg2l_dt_node_to_map+0x164/0x194 pinctrl_dt_to_map+0x218/0x37c create_pinctrl+0x70/0x3d8 While at it, add comments for bitmap_lock and lock. Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Tested-by: Chris Paterson <Chris.Paterson2@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230815131558.33787-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-17pinctrl: cs42l43: Add support for the cs42l43Charles Keepax3-0/+622
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface (Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed for portable applications. It provides a high dynamic range, stereo DAC for headphone output, two integrated Class D amplifiers for loudspeakers, and two ADCs for wired headset microphone input or stereo line input. PDM inputs are provided for digital microphones. Add a basic pinctrl driver which supports driver strength for the various pins, gpios, and pinmux for the 2 multi-function pins. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230804104602.395892-5-ckeepax@opensource.cirrus.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-08-15pinctrl: intel: Switch to use exported namespaceAndy Shevchenko16-9/+18
We already have a few symbols exported in the namespace. Let's do the same for others (except PM for now). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15Merge patch series "Reuse common functions from pinctrl-intel"Andy Shevchenko6-236/+57
Raag Jadav <raag.jadav@intel.com> says: This series exports common pinctrl functions that are used across Intel specific platform drivers to PINCTRL_INTEL namespace and reuses them into Baytrail, Cherryview and Lynxpoint drivers. This helps reduce their code and memory footprint. X86 kernels are fairly unikernels such that pinctrl-intel driver is enabled by most Linux distributions and most Intel specific platform drivers (inside drivers/pinctrl/intel) depend on it. The only exception to this is Lynxpoint. But taking into account its fairly old age, it wouldn't suffer much from pinctrl-intel dependency. bloat-o-meter: ============== Intel: add/remove: 17/10 grow/shrink: 0/0 up/down: 375/-319 (56) Total: Before=9598, After=9654, chg +0.58% Baytrail: add/remove: 1/6 grow/shrink: 0/2 up/down: 41/-441 (-400) Total: Before=16538, After=16138, chg -2.42% Cherryview: add/remove: 1/6 grow/shrink: 2/0 up/down: 90/-272 (-182) Total: Before=18133, After=17951, chg -1.00% Lynxpoint: add/remove: 1/6 grow/shrink: 0/1 up/down: 24/-354 (-330) Total: Before=7836, After=7506, chg -4.21% Link: https://lore.kernel.org/r/20230814060311.15945-1-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-28 01:18:39 +0300