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path: root/drivers/pinctrl/pinctrl-single.c
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2015-11-17pinctrl: Delete unnecessary checksMarkus Elfring1-4/+1
The pinctrl_unregister() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-09-16genirq: Remove irq argument from irq flow handlersThomas Gleixner1-1/+1
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
2015-09-04Merge tag 'pinctrl-v4.3-1' of ↵Linus Torvalds1-10/+4
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
2015-07-28pinctrl: kill off set_irq_flags usageRob Herring1-5/+0
set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: linux-gpio@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-20pinctrl: single: ensure pcs irq will not be forced threadedGrygorii Strashko1-1/+2
The PSC IRQ is requested using request_irq() API and as result it can be forced to be threaded IRQ in RT-Kernel if PCS_QUIRK_HAS_SHARED_IRQ is enabled for pinctrl domain. As result, following 'possible irq lock inversion dependency' report can be seen: ========================================================= [ INFO: possible irq lock inversion dependency detected ] 3.14.43-rt42-00360-g96ff499-dirty #24 Not tainted --------------------------------------------------------- irq/369-pinctrl/927 just changed the state of lock: (&pcs->lock){+.....}, at: [<c0375b54>] pcs_irq_handle+0x48/0x9c but this lock was taken by another, HARDIRQ-safe lock in the past: (&irq_desc_lock_class){-.....} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pcs->lock); local_irq_disable(); lock(&irq_desc_lock_class); lock(&pcs->lock); <Interrupt> lock(&irq_desc_lock_class); *** DEADLOCK *** no locks held by irq/369-pinctrl/927. the shortest dependencies between 2nd lock and 1st lock: -> (&irq_desc_lock_class){-.....} ops: 58724 { IN-HARDIRQ-W at: [<c0090040>] lock_acquire+0x9c/0x158 [<c07065c8>] _raw_spin_lock+0x48/0x58 [<c009edac>] handle_fasteoi_irq+0x24/0x15c [<c009abb0>] generic_handle_irq+0x3c/0x4c [<c000f83c>] handle_IRQ+0x50/0xa0 [<c0008674>] gic_handle_irq+0x3c/0x6c [<c0707a04>] __irq_svc+0x44/0x8c [<c000fc44>] arch_cpu_idle+0x40/0x4c [<c009aadc>] cpu_startup_entry+0x270/0x2e0 [<c06fcbf8>] rest_init+0xd4/0xe4 [<c0a44bfc>] start_kernel+0x3d0/0x3dc [<80008084>] 0x80008084 INITIAL USE at: [<c0090040>] lock_acquire+0x9c/0x158 [<c070674c>] _raw_spin_lock_irqsave+0x54/0x68 [<c009aff8>] __irq_get_desc_lock+0x64/0xa4 [<c009e38c>] irq_set_chip+0x30/0x78 [<c009ec30>] irq_set_chip_and_handler_name+0x24/0x3c [<c036ca10>] gic_irq_domain_map+0x48/0xb4 [<c00a0a80>] irq_domain_associate+0x84/0x1d4 [<c00a1154>] irq_create_mapping+0x80/0x11c [<c00a1270>] irq_create_of_mapping+0x80/0x120 [<c05cdaa8>] irq_of_parse_and_map+0x34/0x3c [<c0a4ea24>] omap_dm_timer_init_one+0x90/0x30c [<c0a4eef0>] omap5_realtime_timer_init+0x8c/0x48c [<c0a486b0>] time_init+0x28/0x38 [<c0a44a6c>] start_kernel+0x240/0x3dc [<80008084>] 0x80008084 } ... key at: [<c1049ce0>] irq_desc_lock_class+0x0/0x8 ... acquired at: [<c07065c8>] _raw_spin_lock+0x48/0x58 [<c0375a90>] pcs_irq_unmask+0x58/0xa0 [<c009ea48>] irq_enable+0x38/0x48 [<c009ead0>] irq_startup+0x78/0x7c [<c009d440>] __setup_irq+0x4a8/0x4f4 [<c009d5dc>] request_threaded_irq+0xb8/0x138 [<c0415a5c>] omap_8250_startup+0x4c/0x148 [<c041276c>] serial8250_startup+0x24/0x30 [<c040d0ec>] uart_startup.part.9+0x5c/0x1b4 [<c040dbcc>] uart_open+0xf4/0x16c [<c03f0540>] tty_open+0x170/0x61c [<c0157028>] chrdev_open+0xbc/0x1b4 [<c0150494>] do_dentry_open+0x1e8/0x2bc [<c0150a84>] finish_open+0x44/0x5c [<c0160d50>] do_last.isra.47+0x710/0xca0 [<c01613a4>] path_openat+0xc4/0x640 [<c0162904>] do_filp_open+0x3c/0x98 [<c0151bdc>] do_sys_open+0x114/0x1d8 [<c0151cc8>] SyS_open+0x28/0x2c [<c0a44d70>] kernel_init_freeable+0x168/0x1e4 [<c06fcc24>] kernel_init+0x1c/0xf8 [<c000eee8>] ret_from_fork+0x14/0x20 -> (&pcs->lock){+.....} ops: 65 { HARDIRQ-ON-W at: [<c0090040>] lock_acquire+0x9c/0x158 [<c07065c8>] _raw_spin_lock+0x48/0x58 [<c0375b54>] pcs_irq_handle+0x48/0x9c [<c0375c5c>] pcs_irq_handler+0x1c/0x28 [<c009c458>] irq_forced_thread_fn+0x30/0x74 [<c009c784>] irq_thread+0x158/0x1c4 [<c0063fc4>] kthread+0xd4/0xe8 [<c000eee8>] ret_from_fork+0x14/0x20 INITIAL USE at: [<c0090040>] lock_acquire+0x9c/0x158 [<c070674c>] _raw_spin_lock_irqsave+0x54/0x68 [<c0375344>] pcs_enable+0x7c/0xe8 [<c0372a44>] pinmux_enable_setting+0x178/0x220 [<c036fecc>] pinctrl_select_state+0x110/0x194 [<c04732dc>] pinctrl_bind_pins+0x7c/0x108 [<c045853c>] driver_probe_device+0x70/0x254 [<c0458810>] __driver_attach+0x9c/0xa0 [<c045674c>] bus_for_each_dev+0x78/0xac [<c0458030>] driver_attach+0x2c/0x30 [<c0457c78>] bus_add_driver+0x15c/0x204 [<c0458ee0>] driver_register+0x88/0x108 [<c045a168>] __platform_driver_register+0x64/0x6c [<c0a8170c>] omap_hsmmc_driver_init+0x1c/0x20 [<c0008a94>] do_one_initcall+0x110/0x170 [<c0a44d48>] kernel_init_freeable+0x140/0x1e4 [<c06fcc24>] kernel_init+0x1c/0xf8 [<c000eee8>] ret_from_fork+0x14/0x20 } ... key at: [<c1088a8c>] __key.18572+0x0/0x8 ... acquired at: [<c008cdd4>] mark_lock+0x388/0x76c [<c008df40>] __lock_acquire+0x6d0/0x1f98 [<c0090040>] lock_acquire+0x9c/0x158 [<c07065c8>] _raw_spin_lock+0x48/0x58 [<c0375b54>] pcs_irq_handle+0x48/0x9c [<c0375c5c>] pcs_irq_handler+0x1c/0x28 [<c009c458>] irq_forced_thread_fn+0x30/0x74 [<c009c784>] irq_thread+0x158/0x1c4 [<c0063fc4>] kthread+0xd4/0xe8 [<c000eee8>] ret_from_fork+0x14/0x20 stack backtrace: CPU: 1 PID: 927 Comm: irq/369-pinctrl Not tainted 3.14.43-rt42-00360-g96ff499-dirty #24 [<c00177e0>] (unwind_backtrace) from [<c00130b0>] (show_stack+0x20/0x24) [<c00130b0>] (show_stack) from [<c0702958>] (dump_stack+0x84/0xd0) [<c0702958>] (dump_stack) from [<c008bcfc>] (print_irq_inversion_bug+0x1d0/0x21c) [<c008bcfc>] (print_irq_inversion_bug) from [<c008bf18>] (check_usage_backwards+0xb4/0x11c) [<c008bf18>] (check_usage_backwards) from [<c008cdd4>] (mark_lock+0x388/0x76c) [<c008cdd4>] (mark_lock) from [<c008df40>] (__lock_acquire+0x6d0/0x1f98) [<c008df40>] (__lock_acquire) from [<c0090040>] (lock_acquire+0x9c/0x158) [<c0090040>] (lock_acquire) from [<c07065c8>] (_raw_spin_lock+0x48/0x58) [<c07065c8>] (_raw_spin_lock) from [<c0375b54>] (pcs_irq_handle+0x48/0x9c) [<c0375b54>] (pcs_irq_handle) from [<c0375c5c>] (pcs_irq_handler+0x1c/0x28) [<c0375c5c>] (pcs_irq_handler) from [<c009c458>] (irq_forced_thread_fn+0x30/0x74) [<c009c458>] (irq_forced_thread_fn) from [<c009c784>] (irq_thread+0x158/0x1c4) [<c009c784>] (irq_thread) from [<c0063fc4>] (kthread+0xd4/0xe8) [<c0063fc4>] (kthread) from [<c000eee8>] (ret_from_fork+0x14/0x20) To fix it use IRQF_NO_THREAD to ensure that pcs irq will not be forced threaded. Cc: Tony Lindgren <tony@atomide.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-17pinctrl: Use irq_desc_get_xxx() to avoid redundant lookup of irq_descJiang Liu1-1/+1
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-17pinctrl: Consolidate chained IRQ handler install/removeThomas Gleixner1-3/+3
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org
2015-07-16pinctrl: single: dra7: remove PCS_QUIRK_SHARED_IRQGrygorii Strashko1-1/+0
On DRA7 there is one pinctrl domain (dra7_pmx_core) and PRCM wake-up IRQ is not shared, so remove quirk. Cc: Nishanth Menon <nm@ti.com> Fixes: 31320beaa3d3 ('pinctrl: single: Add DRA7 pinctrl compatibility') Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: make pinctrl_register() return proper error codeMasahiro Yamada1-2/+2
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Ray Jui <rjui@broadcom.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-06pinctrl: single: Constify irq_domain_opsKrzysztof Kozlowski1-1/+1
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27pinctrl: constify of_device_id arrayFabian Frederick1-2/+2
of_device_id is always used as const. (See driver.of_match_table and open firmware functions) Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-20pinctrl: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-09-05pinctrl: single: fix freudian slipLinus Walleij1-1/+1
commit 03e9f0cac5da6af85758276cb4624caf5911f2b9 "pinctrl: clean up after enable refactoring" renamed the vtable callback .enable to .set_mux. The renaming was done manually, and one of the alterations contained a freudian slip. I confess, I am human. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04pinctrl: clean up after enable refactoringLinus Walleij1-2/+2
commit 2243a87d90b42eb38bc281957df3e57c712b5e56 "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Fan Wu <fwu@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-29pinctrl: single: AM437x: Add pinctrl compatibilityKeerthy1-0/+7
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: Keerthy <j-keerthy@ti.com> [nm@ti.com: minor updates] Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-29pinctrl: single: Add DRA7 pinctrl compatibilityNishanth Menon1-0/+7
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: pinctrl-single.c: Cleaning up wrong format string usageRickard Strandqvist1-1/+1
%d in format string used, but the type is unsigned int This was found using a static code analysis program called cppcheck Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: pinctrl-single.c: Cleaning up values that are never usedRickard Strandqvist1-2/+1
Remove variable that are never used This was found using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: avoid duplicated calling enable_pinmux_setting for a pinFan Wu1-56/+0
What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: single: Clear pin interrupts enabled by bootloaderTony Lindgren1-0/+13
Since we set up device wake-up interrupts as pinctrl-single interrupts, we now must use the standard request_irq and related functions to manage them. If the pin interrupts are enabled for some pins at boot, the wake-up events can show up as constantly pending at least on omaps and will hang the system unless the related device driver clears the event at the device. To fix this, let's clear the interrupt flags during init, and print out a warning so the board maintainers can update their drivers to do proper request_irq for the driver specific wake-up events. Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: single: add low power mode supportChao Xie1-0/+3
For some silicons, the pin configuration register can control the output of the pin when the pad including the pin enter low power mode. For example, the pin can be "Drive 1", "Drive 0", "Float" when the pad including the pin enter low power mode. It is very useful when you want to control the power leakeage when the SOC enter low power mode, and can save more power for the low power mode. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15pinctrl: single: fix infinite loop caused by bad maskTomi Valkeinen1-0/+8
commit 4e7e8017a80e1 (pinctrl: pinctrl-single: enhance to configure multiple pins of different modules) improved support for pinctrl-single,bits option, but also caused a regression in parsing badly configured mask data. If the masks in DT data are not quite right, pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop, trashing memory at the same time. Add a check to verify that each loop actually removes bits from the 'mask', so that the loop can eventually end. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-15pinctrl: single: fix pcs_disable with bits_per_muxTomi Valkeinen1-2/+8
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is enabled. However, pcs_disable() always uses pcs->fmask. Fix pcs_disable() to use vals->mask with bits_per_mux. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-14pinctrl: single: call pcs_soc->rearm() whenever IRQ mask is changedRoger Quadros1-7/+3
On OMAPs the IO ring must be rearmed each time the pad wakeup configuration is changed. So call pcs_soc->rearm() from pcs_irq_set(). As pinctrl-single is now an interrupt controller in some cases, we should follow the standards and keep the interrupts enabled constantly, and not just for wake-up events. The tracking of runtime vs wake-up interrupts can be handled separately for the automated runtime PM solution when we have it in the future. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> [tony@atomide.com: removed wrong comment, updated description] Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-19pinctrl: single: Fix build when not built on ARMTony Lindgren1-1/+6
Looks like we need a little bit of arch specific handling with the generic IRQ. Fix the issue with an ifdef the same way as other drivers do. ARM needs things set to IRQF_VALID, which also then sets noprobe. Others seem to use just irq_set_noprobe(). Otherwise we can get: drivers/pinctrl/pinctrl-single.c: In function 'pcs_irqdomain_map': drivers/pinctrl/pinctrl-single.c:1750:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pinctrl/pinctrl-single.c:1750:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pinctrl/pinctrl-single.c:1750:34: error: 'IRQF_PROBE' undeclared (first use in this function) Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-11pinctrl: single: Add support for auxdataTony Lindgren1-0/+23
For omaps, we still have dependencies to the legacy code for handling the PRM (Power Reset Management) interrupts, and also for reconfiguring the io wake-up chain after changes. Let's pass the PRM interrupt and the rearm functions via auxdata. Then when at some point we have a proper PRM driver, we can get the interrupt via device tree and set up the rearm function as exported function in the PRM driver. By using auxdata we can remove a dependency to the wake-up events for converting omap3 to be device tree only. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: linux-kernel@vger.kernel.org Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-11pinctrl: single: Add support for wake-up interruptsTony Lindgren1-0/+322
The pin control registers can have interrupts for example for device wake-up. These interrupts can be treated as a chained interrupt controller as suggested earlier by Linus Walleij <linus.walleij@linaro.org>. This patch adds support for interrupts in a way that should be pretty generic, and works for the omaps that support wake-up interrupts. On omaps, there's an interrupt enable and interrupt status bit for each pin. The two pinctrl domains on omaps share a single interrupt from the PRM chained interrupt handler. Support for other similar hardware should be easy to add. Note that this patch does not attempt to handle the wake-up interrupts automatically unlike the earlier patches. This patch allows the device drivers to do a request_irq() on the wake-up pins as needed. I'll try to do also a separate generic patch for handling the wake-up events automatically. Also note that as this patch makes the pinctrl-single an irq controller, the current bindings need some extra trickery to use interrupts from two different interrupt controllers for the same driver. So it might be worth waiting a little on the patches enabling the wake-up interrupts from drivers as there should be a generic way to handle it coming. And also there's been discussion of interrupts-extended binding for using interrupts from multiple interrupt controllers. In any case, this patch should be ready to go allowing handling the wake-up interrupts in a generic way, or separately from the device drivers. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: linux-kernel@vger.kernel.org Cc: Benoît Cousson <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-10pinctrl: single: Prepare for supporting SoC specific featuresTony Lindgren1-9/+29
Let's replace is_pinconf with flags and add struct pcs_soc_data so we can support SoC specific features like pin wake-up events. Done in collaboration with Roger Quadros <rogerq@ti.com>. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: linux-kernel@vger.kernel.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-08-29Merge tag 'v3.11-rc7' into develLinus Walleij1-0/+2
Merged in this to avoid conflicts with the big locking fixes from upstream. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/pinctrl/pinctrl-sunxi.c
2013-08-28pinctrl: Pass all configs to driver on pin_config_set()Sherman Yin1-11/+22
When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Matt Porter <matt.porter@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-23pinctrl: pinctrl-single: fix compile warning when no CONFIG_PMJean-Francois Moine1-0/+2
This warning has been introduced by the commit 0f9bc4bcdf4f pinctrl: single: adopt pinctrl sleep mode management Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17pinctrl: single: adopt pinctrl sleep mode managementHebbar Gururaja1-0/+27
Make pinctrl-single able to handle suspend/resume events and change hogged pins states accordingly. Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: pinctrl-single: pin names for pinctrl-single.bitsManjunathappa, Prakash1-5/+10
Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: pinctrl-single: enhance to configure multiple pins of different modulesManjunathappa, Prakash1-33/+165
Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb68a21d5704839a192a46ebcf387773704), Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-14pinctrl: single: fix error return code in pcs_parse_one_pinctrl_entry()Wei Yongjun1-1/+2
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Introduced by commit 9dddb4df90d136429b6d6ddefceb49a9b93f6cd1 (pinctrl: single: support generic pinconf) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-13pinctrl: single: correct argument for pinconfHaojian Zhuang1-8/+8
pcs_pinconf_set() is always using "arg << shift" to configure two parameters case. But pcs_add_conf2() didn't remove shift for config argument. So correct it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: single: Fix build errorAxel Lin1-3/+3
If pcs->is_pinconf is false, it means does not support pinconf. If pcs->is_pinconf is true, is_generic flag is always true. This patch fixes below build error: CC [M] drivers/pinctrl/pinctrl-single.o drivers/pinctrl/pinctrl-single.c: In function 'pcs_probe': drivers/pinctrl/pinctrl-single.c:1441:3: error: assignment of member 'is_generic' in read-only object make[2]: *** [drivers/pinctrl/pinctrl-single.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: single: support generic pinconfHaojian Zhuang1-7/+401
Support the operation of generic pinconf. The supported config arguments are INPUT_SCHMITT, INPUT_SCHMITT_ENABLE, DRIVE_STRENGHT, BIAS_DISABLE, BIAS_PULLUP, BIAS_PULLDOWN, SLEW_RATE. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: single: set function mask as optionalHaojian Zhuang1-4/+22
Since Hisilicon's pin controller is divided into two parts. One is the function mux, and the other is pin configuration. These two parts are in the different memory regions. So make pinctrl-single,function-mask as optional property. Then we can define pingroups without valid function mux that is only used for pin configuration. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: single: create new gpio function rangeHaojian Zhuang1-2/+71
Since gpio driver could create gpio range in DTS, it could invoke pinctrl_request_gpio(). In the pinctrl-single driver, it needs to configure pins with gpio function mode. A new gpio function range should be created in DTS file in below. pinctrl-single,gpio-range = <phandle pin_offset nr_pins gpio_func>; range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; }; The gpio-ranges property is used in gpio driver and the pinctrl-single,gpio-range property is used in pinctrl-single driver. 1. gpio-ranges is used for gpio driver in below. gpio-ranges = <phandle gpio_offset_in_chip pin_offset nr_pins> gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; 2. gpio driver could get pin offset from gpio-ranges property. pinctrl-single driver could get gpio function mode from gpio_func that is stored in @gpiofuncs list in struct pcs_device. This new pinctrl-single,gpio-range is used as complement for gpio-ranges property in gpio driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: Declare operation structures as constLaurent Pinchart1-3/+3
The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22Revert "pinctrl: single: support gpio request and free"Haojian Zhuang1-77/+2
This reverts commit 2e8b2eab94c35d83bb7da71c63b4695f32ddca88. Conflicts: drivers/pinctrl/pinctrl-single.c ERROR: "__aeabi_uldivmod" [drivers/pinctrl/pinctrl-single.ko] undefined!] On Fri, Jan 11, 2013 at 4:00 PM, Russell King wrote: > The above error happens in builds including pinctrl-single - the > reason > is this, where resource_size_t may be 64-bit. > > gpio->range.pin_base = (r.start - pcs->res->start) / > mux_bytes; > gpio->range.npins = (r.end - r.start) / mux_bytes + 1; The reason of not fixing this issue and reverting the patch instead is this patch can't handle another case. It's not easy to handle multiple gpios sharing one pin register. So this gpio range feature will be implemented by other patches. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-04Drivers: pinctrl: remove __dev* attributes.Greg Kroah-Hartman1-5/+4
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Barry Song <baohua.song@csr.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-12Merge tag 'driver-core-3.8-rc1' of ↵Linus Torvalds1-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg Kroah-Hartman: "Here's the large driver core updates for 3.8-rc1. The biggest thing here is the various __dev* marking removals. This is going to be a pain for the merge with different subsystem trees, I know, but all of the patches included here have been ACKed by their various subsystem maintainers, as they wanted them to go through here. If this is too much of a pain, I can pull all of them out of this tree and just send you one with the other fixes/updates and then, after 3.8-rc1 is out, do the rest of the removals to ensure we catch them all, it's up to you. The merges should all be trivial, and Stephen has been doing them all in linux-next for a few weeks now quite easily. Other than the __dev* marking removals, there's nothing major here, some firmware loading updates and other minor things in the driver core. All of these have (much to Stephen's annoyance), been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>" Fixed up trivial conflicts in drivers/gpio/gpio-{em,stmpe}.c due to gpio update. * tag 'driver-core-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (93 commits) modpost.c: Stop checking __dev* section mismatches init.h: Remove __dev* sections from the kernel acpi: remove use of __devinit PCI: Remove __dev* markings PCI: Always build setup-bus when PCI is enabled PCI: Move pci_uevent into pci-driver.c PCI: Remove CONFIG_HOTPLUG ifdefs unicore32/PCI: Remove CONFIG_HOTPLUG ifdefs sh/PCI: Remove CONFIG_HOTPLUG ifdefs powerpc/PCI: Remove CONFIG_HOTPLUG ifdefs mips/PCI: Remove CONFIG_HOTPLUG ifdefs microblaze/PCI: Remove CONFIG_HOTPLUG ifdefs dma: remove use of __devinit dma: remove use of __devexit_p firewire: remove use of __devinitdata firewire: remove use of __devinit leds: remove use of __devexit leds: remove use of __devinit leds: remove use of __devexit_p mmc: remove use of __devexit ...
2012-11-28pinctrl: remove use of __devexitBill Pemberton1-1/+1
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-28pinctrl: remove use of __devinitdataBill Pemberton1-1/+1
CONFIG_HOTPLUG is going away as an option so __devinitdata is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-28pinctrl: remove use of __devexit_pBill Pemberton1-1/+1
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-23pinctrl: pinctrl-single: Fix error check conditionSachin Kamat1-1/+1
*map should be tested for NULL instead of map. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-21pinctrl: single: support gpio request and freeHaojian Zhuang1-2/+78
Marvell's PXA/MMP silicon also match the behavior of pinctrl-single. Each pin binds to one register. A lot of pins could be configured as gpio. GPIO range is defined as a child node of pinmux in .dtsi file. If those pins are with the same gpio function configuration in the pinmux register, they could be defined in the same GPIO range. For this new child node, two properties are used. reg = <the start of pinmux register in range, size of range> pinctrl-single,gpio: <gpio base in range, the gpio function of the range in the pinmux register> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-15pinctrl: single: dump pinmux register valueHaojian Zhuang1-4/+4
Dump pinmux register value, not only function part in the pinmux register. Also fix the issue on caluclating pin offset. The last parameter should be pin number, not register offset. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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