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2020-01-29Merge tag 'usb-5.6-rc1' of ↵Linus Torvalds29-579/+3048
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/Thunderbolt/PHY driver updates from Greg KH: "Here is the big USB and Thunderbolt and PHY driver updates for 5.6-rc1. With the advent of USB4, "Thunderbolt" has really become USB4, so the renaming of the Kconfig option and starting to share subsystem code has begun, hence both subsystems coming in through the same tree here. PHY driver updates also touched USB drivers, so that is coming in through here as well. Major stuff included in here are: - USB 4 initial support added (i.e. Thunderbolt) - musb driver updates - USB gadget driver updates - PHY driver updates - USB PHY driver updates - lots of USB serial stuff fixed up - USB typec updates - USB-IP fixes - lots of other smaller USB driver updates All of these have been in linux-next for a while now (the usb-serial tree is already tested in linux-next on its own before merged into here), with no reported issues" [ Removed an incorrect compile test enablement for PHY_EXYNOS5250_SATA that causes configuration warnings - Linus ] * tag 'usb-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (207 commits) Doc: ABI: add usb charger uevent usb: phy: show USB charger type for user usb: cdns3: fix spelling mistake and rework grammar in text usb: phy: phy-gpio-vbus-usb: Convert to GPIO descriptors USB: serial: cyberjack: fix spelling mistake "To" -> "Too" USB: serial: ir-usb: simplify endpoint check USB: serial: ir-usb: make set_termios synchronous USB: serial: ir-usb: fix IrLAP framing USB: serial: ir-usb: fix link-speed handling USB: serial: ir-usb: add missing endpoint sanity check usb: typec: fusb302: fix "op-sink-microwatt" default that was in mW usb: typec: wcove: fix "op-sink-microwatt" default that was in mW usb: dwc3: pci: add ID for the Intel Comet Lake -V variant usb: typec: tcpci: mask event interrupts when remove driver usb: host: xhci-tegra: set MODULE_FIRMWARE for tegra186 usb: chipidea: add inline for ci_hdrc_host_driver_init if host is not defined usb: chipidea: handle single role for usb role class usb: musb: fix spelling mistake: "periperal" -> "peripheral" phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESS USB: usbfs: Always unlink URBs in reverse order ...
2020-01-20Merge ra.kernel.org:/pub/scm/linux/kernel/git/netdev/netDavid S. Miller4-47/+98
2020-01-18phy: ti: j721e-wiz: Fix build error without CONFIG_OF_ADDRESSHongbo Yao1-0/+1
If CONFIG_OF_ADDRESS is not set and COMPILE_TEST=y, the following error is seen while building phy-j721e-wiz.c drivers/phy/ti/phy-j721e-wiz.o: In function `wiz_remove': phy-j721e-wiz.c:(.text+0x1a): undefined reference to `of_platform_device_destroy' Fix the config dependency for PHY_J721E_WIZ here. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Hongbo Yao <yaohongbo@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200117212310.2864-1-kishon@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-17Merge tag 'phy-for-5.6_v2' of ↵Greg Kroah-Hartman25-566/+3027
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.6 *) Add support in PHY core to create link between PHY consumer and PHY provider *) Add DisplayPort PHY configuration set to be used for negotiating the configurations to be used between DisplayPort controller and DisplayPort PHY *) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for J721E SoC (Supports USB and PCIe) *) Add PHY driver for eMMC PHY in Intel LGM SoC *) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new Synopsys USB Controller *) Add support for 16nm SATA PHY present in Broadcom 7216 SoC *) Fix lost packet issue, fix MDIO from getting inaccessible, fix occasional transaction failures, fix USB driver from crashing in Broadcom USB PHY driver *) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150 *) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from display controller to rockchip-inno-dsidphy *) Other cleanups including compile testing for some of the PHY drivers, fixing Kconfig indentation, duplicate writes in drivers etc., Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits) dt-bindings: phy: Add PHY_TYPE_DP definition phy: ti: j721e-wiz: Fix return value check in wiz_probe() dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE phy: ti: j721e-wiz: Manage typec-gpio-dir dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: cadence: Sierra: add phy_reset hook phy: cadence: Sierra: remove redundant initialization of pointer regmap phy: Add DisplayPort configuration options phy: Enable compile testing for some of drivers phy: mediatek: Fix Kconfig indentation phy: intel-lgm-emmc: Add support for eMMC PHY dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Get reset control "array" for each link ...
2020-01-17phy: ti: j721e-wiz: Fix return value check in wiz_probe()Wei Yongjun1-1/+1
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSERamuthevar Vadivel Murugan1-0/+1
commit 95f1061f715e ("phy: intel-lgm-emmc: Add support for eMMC PHY") introduces the below warning WARNING: modpost: missing MODULE_LICENSE() in drivers/phy/intel/phy-intel-emmc.o Fix it by adding missing MODULE_LICENSE. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: ti: j721e-wiz: Manage typec-gpio-dirRoger Quadros1-0/+61
Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: cadence: Sierra: add phy_reset hookRoger Quadros1-0/+10
Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King1-1/+1
The pointer regmap is being initialized with a value that is never read and it is being updated later with a new value from phy->regmap_common_cdb. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: Enable compile testing for some of driversKrzysztof Kozlowski6-15/+21
Some of the phy drivers can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: mediatek: Fix Kconfig indentationKrzysztof Kozlowski1-10/+10
Adjust indentation from spaces to tab (+optional two spaces) as in coding style. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: intel-lgm-emmc: Add support for eMMC PHYRamuthevar Vadivel Murugan5-0/+296
Add support for eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCKishon Vijay Abraham I3-0/+914
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig), two divider clocks and supports resets for each of the lanes. [jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper] Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-13Merge 5.5-rc6 into usb-nextGreg Kroah-Hartman4-47/+98
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-08phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I1-1/+1
commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency ↵Kishon Vijay Abraham I1-0/+21
to 25MHz Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I1-1/+21
Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I1-1/+32
Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I1-1/+1
A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ↵Anil Varughese1-96/+254
external SSC The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese <aniljoy@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Modify register macro names to be in sync with Sierra ↵Kishon Vijay Abraham I1-83/+84
user guide No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I1-6/+9
Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I1-0/+14
SERDES_16G in TI's J721E SoC uses Cadence Sierra PHY. Add support to use Cadence Sierra driver in J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Use "regmap" for read and write to Sierra registersKishon Vijay Abraham I1-54/+237
Use "regmap" for read and write to Sierra registers. This is in perparation for adding SERDES_16G support present in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resourcesKishon Vijay Abraham I1-2/+2
Certain platforms like TI J721E using Cadence Sierra Serdes doesn't provide explicit phy_clk and reset (APB reset) control. Make them optional here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Add support for wake and USB low power mode for 7211 S2/S5Al Cooper4-34/+105
Add support for 7211 USB wake. Disable all possible 7211 USB logic for S2/S5 if USB wake is not enabled. On the 7211, the XHCI wake signal was not connected properly and only goes to the USB1_USB1_CTRL_TP_DIAG1 diagonstic register. The workaround is to have VPU code running that polls for the proper bit in the DIAG register and to wake the system when the bit is asserted. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: USB driver is crashing during S3 resume on 7216Al Cooper1-1/+1
This is a result of the USB 2.0 clocks not being disabled/enabled during suspend/resume on XHCI only systems. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: bdc: Fix occasional failure with BDC on 7211Al Cooper3-4/+38
The BDC "Read Transaction Size" needs to be changed from 1024 bytes to 256 bytes to prevent occasional transaction failures. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: PHY's MDIO registers not accessible without device installedAl Cooper1-0/+9
When there is no device connected and FSM is enabled, the XHCI puts the PHY into suspend mode. When the PHY is put into suspend mode the USB LDO powers down the PHY. This causes the MDIO to be inaccessible and its registers reset to default. The fix is to disable FSM. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: fix driver to defer on clk_get deferAl Cooper1-0/+6
Handle defer on clk_get because the new SCMI clock driver comes up after this driver. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Add support for new Synopsys USB controller on the 7211b0Al Cooper4-78/+295
The 7211b0 has added the STB XHCI Synopsys controller and it will be used instead of the RPi based DWC USB controller. The new Synopsys XHCI controller core is the same one that is used on the 7216, but because of the way the STB USB PHY is used on both the A0 and B0, some of the PHY control is different. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Add support for new Synopsys USB controller on the 7216Al Cooper4-18/+227
The 7216 has the new USB XHCI controller from Synopsys. While this new controller and the PHY are similar to the STB versions, the major differences are: - Many of the registers and fields in the CTRL block have been removed or changed. - A new set of Synopsys control registers, BCHP_USB_XHCI_GBL, were added. - MDIO functionality has been replaced with direct access registers in the BCHP_USB_XHCI_GBL block. - Power up PHY defaults that had to be changed by MDIO in previous chips will now power up with the correct defaults. A new init module was created for this new Synopsys USB controller. A new compatible string was added and the driver will dispatch into one of two init modules based on it. A "reg-names" field was added so the driver can more easily get optional registers. A DT bindings document was also added for this driver. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Restructure in preparation for adding 7216 USB supportAl Cooper3-123/+214
The driver is being restructured in preparation for adding support for the new Synopsys USB conroller on the 7216. Since all the bugs and work-arounds in previous STB chips are supposed to be fixed, most of the code in phy-brcm-usb-init.c is not needed. Instead of adding more complexity to the already complicated phy-brcm-usb-init.c module, the driver will be restructured to use a vector table to dispatch into different C modules for the different controllers. There was also some general cleanup done including some ipp setup code that was incorrect. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Add "wake on" functionalityAl Cooper3-3/+63
Add the ability to handle USB wake events from USB devices when in S2 mode. Typically there is some additional configuration needed to tell the USB device to generate the wake event when suspended but this varies with the different USB device classes. For example, on USB Ethernet dongles, ethtool should be used to enable the magic packet wake functionality in the dongle. NOTE: This requires that the "power/wakeup" sysfs entry for the USB device generating the wakeup be set to "enabled". This functionality requires a special hardware sideband path that will trigger the AON_PM_L2 interrupt needed to wake the system from S2 even though the USB host controllers are in IDDQ (low power state) and most USB related clocks are shut off. For the sideband signaling to work we need to leave the usbx_freerun clock running, but this clock consumes very little power by design. There's a bug in the XHCI wake hardware so only EHCI/OHCI wake is currently supported. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Put USB phys into IDDQ on suspend to save power in S2 modeAl Cooper2-4/+9
Currently the Phy driver will put the USB phys into the max power saving mode (IDDQ) when there is no corresponding XHCI, EHCI or OHCI client (through rmmod, unbind or if the driver is not builtin). This change will also put the Phys into IDDQ mode on suspend so that S2 will get the additional power savings. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: Get all drivers that use USB clks using correct enable/disableAl Cooper1-14/+14
The BRCM USB Phy, ohci, ehci and xhci drivers all use the USB clocks but not all drivers use the clk_prepare_enable/clk_disable_unprepare versions to enable/disable the clocks. This change gets all drivers using the prepare version. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: usb: EHCI DMA may lose a burst of DMA data for 7255xA0 familyAl Cooper1-0/+13
When the EHCI controller received a 512 byte USB packet that had to be broken into 2 256 byte bursts across the SCB bus AND there was a following 512 byte USB packet, the second burst of data from the first packet was sometimes being lost. If the burst size was changed to 128 bytes via the EBR_SCB_SIZE field in the USB_CTRL_EBRIDGE register we'd see the 4th 128 byte burst of the first packet being lost. This problem became much worse if other threads were running that accessed memory, like a memcpy test. Setting the EBR_SCB_SIZE to 512, which prevents breaking the EHCI USB packet (max size of 512 bytes) into bursts, fixed the problem. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: qcom-qmp: Add SW reset registerVinod Koul1-0/+1
For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and then deassert it, so add the QPHY_SW_RESET register which does this. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Can Guo <cang@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: qcom-qmp: remove no_pcs_sw_reset for sm8150Vinod Koul1-1/+0
SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's PCS register so we should not mark no_pcs_sw_reset for sm8150 and onwards Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Can Guo <cang@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: qcom-qmp: remove duplicate powerdown writeVinod Koul1-1/+0
We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init() before invoking qcom_qmp_phy_configure() so remove the duplicate write. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: qcom-qmp: Use register definesVinod Koul1-2/+2
We already define register offsets so use them in register layout. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Can Guo <cang@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: brcm-sata: Implement 7216 initialization sequenceFlorian Fainelli1-0/+120
7216 is a 16nm process chip with a slightly different version of the PHY SerdDeS/AFE that requires a specific tuning sequence. Key on the compatible string to perform that initialization. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy/rockchip: inno-dsidphy: generalize parameter handlingHeiko Stuebner2-220/+100
During review it came to light that exposing the pll clock outside is not the right approach and struct phy_configure_opts_mipi_dphy exists just for that reason to transfer parameters to the phy. So drop the exposed clock and rely on the phy configure options to bring in the correct rate. That way we can also just drop the open coded timing struct and default values function. Fixes: b7535a3bc0ba ("phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY") Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: lantiq: vrx200-pcie: Remove unneeded semicolonMa Feng1-1/+1
Fixes coccicheck warning: drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ma Feng <mafeng.ma@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: qualcomm: Adjust indentation in read_poll_timeoutNathan Chancellor1-1/+1
Clang warns: ../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:83:4: warning: misleading indentation; statement is not part of the previous 'if' [-Wmisleading-indentation] usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); ^ ../drivers/phy/qualcomm/phy-qcom-apq8064-sata.c:80:3: note: previous statement is here if (readl_relaxed(addr) & mask) ^ 1 warning generated. This warning occurs because there is a space after the tab on this line. Remove it so that the indentation is consistent with the Linux kernel coding style and clang no longer warns. Fixes: 1de990d8a169 ("phy: qcom: Add driver for QCOM APQ8064 SATA PHY") Link: https://github.com/ClangBuiltLinux/linux/issues/816 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: core: Add consumer device link supportAlexandre Torgue1-5/+44
In order to enforce suspend/resume ordering, this commit creates link between phy consumers and phy devices. This link avoids to suspend phy before phy consumers. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> [jonathanh@nvidia.com: Fix an abort when of_phy_get() returns error] Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-06phy: Enable compile testing for some of driversKrzysztof Kozlowski6-15/+22
Some of the phy drivers can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200103164710.4829-2-krzk@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-06net: switch to using PHY_INTERFACE_MODE_10GBASER rather than 10GKRRussell King1-10/+10
Switch network drivers, phy drivers, and SFP/phylink over to use the more correct 10GBASE-R, rather than 10GBASE-KR. 10GBASE-KR is backplane ethernet, which is 10GBASE-R with autonegotiation on top, which our current usage on the affected platforms does not have. The only remaining user of PHY_INTERFACE_MODE_10GKR is the Aquantia PHY, which has a separate mode for 10GBASE-KR. For Marvell mvpp2, we detect 10GBASE-KR, and rewrite it to 10GBASE-R for compatibility with existing DT - this is the only network driver at present that makes use of PHY_INTERFACE_MODE_10GKR. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-12-31phy/rockchip: inno-hdmi: round clock rate down to closest 1000 HzJonas Karlman1-0/+4
Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") changed what rate clk_round_rate() is called with, an additional 999 Hz added to the requsted mode clock. This has caused a regression on RK3328 and presumably also on RK3228 because the inno-hdmi-phy clock requires an exact match of the requested rate in the pre pll config table. When an exact match is not found the parent clock rate (24MHz) is returned to the clk_round_rate() caller. This cause wrong pixel clock to be used and result in no-signal when configuring a mode on RK3328. Fix this by rounding the rate down to closest 1000 Hz in round_rate func, this allows an exact match to be found in pre pll config table. Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-12-26phy: cpcap-usb: Drop extra write to usb2 registerTony Lindgren1-6/+0
We are currently writing the same register twice. Let's enable the USB PHY only at the end of the function. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-27 08:57:39 +0300