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path: root/drivers/phy/phy-mt65xx-usb3.c
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2017-08-20phy: phy-mt65xx-usb3: add mediatek directory and rename fileChunfeng Yun1-1081/+0
The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-20phy: phy-mt65xx-usb3: add SATA PHY supportRyder Lee1-4/+129
This patch adds SATA setting part. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-20phy: phy-mt65xx-usb3: add PCIe PHY supportRyder Lee1-18/+202
This patch adds PCIe PHY setting part. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS portChunfeng Yun1-14/+10
There will be a problem if SS port is diasbled and HS port extracts 100uA from SS port, so disable extract 100uA from SS port in the case, when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port only works on LS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: add support for new version phyChunfeng Yun1-128/+218
There are some variations from mt2701 to mt2712: 1. banks shared by multiple ports are put back into each port, such as SPLLC and U2FREQ; 2. add a new bank MISC for u2port, and CHIP for u3port; 3. bank's offset in each port are also rearranged; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: move clock from phy node into port nodesChunfeng Yun1-2/+25
each port has its own reference clock, the HighSpeed port is 48M, and the SuperSpeed port is usually 26M, put them into port node for flexibility, this can close clock if the port is not used. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: split SuperSpeed port into two onesChunfeng Yun1-74/+75
Currently usb3 port in fact includes two sub-ports, but it is not flexible for some cases, such as following one: usb3 port0 includes u2port0 and u3port0; usb2 port0 includes u2port1; If wants to support only HS, we can use u2port0 or u2port1, when select u2port0, u3port0 is not needed; If wants to support SS, we can compound u2port0 and u3port0, or u2port1 and u3port0, if select latter one, u2port0 is not needed. So it's more flexible to split usb3 port into two ones and also try best to save power by disabling unnecessary ports. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: increase LFPS filter thresholdChunfeng Yun1-0/+9
Increase LFPS filter threshold to avoid some fake remote wakeup signal which cause U3 link fail and link to U2 only at about 0.01% probability. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: improve RX detection stable timeChunfeng Yun1-0/+18
The default value of RX detection stable time is 10us, and this margin is too big for some critical cases which cause U3 link fail and link to U2(probability is about 1%). So change it to 5us. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-01-16drivers: phy: constify phy_ops structuresBhumika Goyal1-1/+1
Declare phy_ops structures as const as they are only passed as an argument to the function devm_phy_create. This argument is of type const struct phy_ops *, so phy_ops structures having this property can be declared as const. Done using Coccinelle: Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2016-04-30phy: phy-mt65xx-usb3: add support for mt2701 platformChunfeng Yun1-25/+52
Add a new OF device ID for mt2701 Some register settings to avoid RX sensitivity level degradation which may arise on mt8173 platform are separated from other platforms. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20phy: phy-mt65xx-usb3: improve HS eye diagramChunfeng Yun1-3/+96
calibrate HS slew rate and switch 100uA current to SSUSB to improve HS eye diagram of HQA test. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20phy: phy-mt65xx-usb3: fix test fail of HS receiver sensitivityChunfeng Yun1-2/+5
when use the default value 8 of RG_USB20_SQTH, the HS receiver sensitivity test of HQA will fail, set it as 2 to fix up the issue. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-03phy: mt65xx-usb3: add missing of_node_putJulia Lawall1-7/+13
for_each_child_of_node performs an of_node_get on each iteration, so a return from the middle of the loop requires an of_node_put. A simplified version of the semantic patch that finds this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | * return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-10-06phy: add usb3.0 phy driver for mt65xx SoCsChunfeng Yun1-0/+506
support usb3.0 phy of mt65xx SoCs Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>