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2017-07-04Merge branch 'pci/host-qcom' into nextBjorn Helgaas1-58/+377
* pci/host-qcom: PCI: qcom: Limit TLP size to 2K to work around hardware issue PCI: qcom: Fix spelling mistake: "asser" -> "assert" PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc PCI: qcom: Add support for IPQ4019 PCIe controller
2017-07-04Merge branch 'pci/host-kirin' into nextBjorn Helgaas3-0/+528
* pci/host-kirin: PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver
2017-07-03Merge branch 'pci/host-imx6' into nextBjorn Helgaas1-1/+36
* pci/host-imx6: PCI: imx6: Add regulator support
2017-07-03Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2-2/+3
* pci/host-dra7xx: PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
2017-07-03Merge branch 'pci/host-designware' into nextBjorn Helgaas11-15/+17
* pci/host-designware: PCI: dwc: Constify dw_pcie_host_ops structures PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
2017-07-03Merge branch 'pci/irq-fixups' into nextBjorn Helgaas1-19/+24
* pci/irq-fixups: arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq() PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions PCI: altera: Drop pci_fixup_irqs() PCI: versatile: Drop pci_fixup_irqs() PCI: generic: Drop pci_fixup_irqs() PCI: faraday: Drop pci_fixup_irqs() PCI: designware: Drop pci_fixup_irqs() PCI: iproc: Drop pci_fixup_irqs() PCI: rcar: Drop pci_fixup_irqs() PCI: xilinx: Drop pci_fixup_irqs() PCI: tegra: Drop pci_fixup_irqs() ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers PCI: Add a call to pci_assign_irq() in pci_device_probe() OF/PCI: Update of_irq_parse_and_map_pci() comment PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it PCI: Add IRQ mapping function pointers to pci_host_bridge struct PCI: Build setup-irq.o on all arches PCI: Remove pci_scan_root_bus_msi() PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge() ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: Make pci_register_host_bridge() PCI core internal PCI: Add pci_scan_root_bus_bridge() interface PCI: tegra: Fix host bridge memory leakage PCI: faraday: Fix host bridge memory leakage PCI: Add devm_pci_alloc_host_bridge() interface PCI: Add pci_free_host_bridge() interface PCI: Initialize bridge release function at bridge allocation PCI: faraday: Convert IRQ masking to raw PCI config accessors PCI: iproc: Convert link check to raw PCI config accessors PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter
2017-07-03PCI: qcom: Limit TLP size to 2K to work around hardware issueSrinivas Kandagatla1-0/+13
Limit TLP size to 2K to work around a hardware bug in the v0 version of PCIe IP. When using default TLP size of 4K, the internal buffer gets corrupted due to this hardware bug. This bug was originally noticed during ssh session between APQ8064-based board and PC. Network packets got corrupted randomly and terminated the ssh session due to this bug. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-03PCI: qcom: Fix spelling mistake: "asser" -> "assert"Colin Ian King1-1/+1
Trivial fix to spelling mistake in dev_err message. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-03PCI: qcom: Reorder to put v0 functions together, v1 functions together, etcBjorn Helgaas1-61/+61
Previously the v0, v1, and v2 functions were not grouped together in a consistent order. Reorder them to make them consistent. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-03PCI: qcom: Add support for IPQ4019 PCIe controllerJohn Crispin1-0/+306
Add support for the IPQ4019 PCIe controller. IPQ4019 supports Gen 1/2, one lane, one PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the same as for the MSM8996, however the clocks and reset lines differ. [bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile issues] Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Rob Herring <robh@kernel.org> # binding
2017-07-03PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driverXiaowei Song3-0/+528
Hisilicon PCIe driver shares the common functions for PCIe dw-host. The poweron functions are developed on hi3660 SoC, while other functions are common for Kirin series SoCs. Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature are not supported currently. Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/20170704021516.96575-1-songxiaowei@hisilicon.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Cc: Guodong Xu <guodong.xu@linaro.org>
2017-07-03PCI: imx6: Add regulator supportQuentin Schulz1-1/+36
Some boards might require to control a regulator to power the PCIe port. Add support for an optional regulator defined in Device Tree linked in the PCIe controller under `vpcie-supply`. If present, the regulator will be disabled and then enabled as part of the PCIe host initialization process and will be disabled when shutting down. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> [bhelgaas: use dev_err() instead of pr_err() in imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2017-07-03PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAINArvind Yadav1-2/+2
Previously, we tried to clear interrupt requests by clearing bits in the PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN registers. But per the TRM, these fields are RW1C, so we must *set* bits to clear the interrupt bits. Fixes: 47ff3de911a7 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-03PCI: dwc: dra7xx: Depend on appropriate SoC or compile testPeter Robinson1-0/+1
The PCI controller attached to a SoC isn't much use if the core SoC isn't enabled, unless of course it's compile testing, so add appropriate dependency. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-03PCI: dwc: Constify dw_pcie_host_ops structuresJisheng Zhang11-13/+13
The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-03PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREADJisheng Zhang2-2/+4
Similar as commit 8ff0ef996ca0 ("PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD"), we should mark PCIe/PCI (MSI) IRQ cascade handlers in designware, qcom, and vmd as IRQF_NO_THREAD explicitly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> # vmd Acked-by: Jingoo Han <jingoohan1@gmail.com> # pcie-designware-plat.c
2017-07-03PCI: designware: Drop pci_fixup_irqs()Lorenzo Pieralisi1-5/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI designware host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-07-03PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-14/+22
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI designware host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-05-23PCI: imx6: Fix config read timeout handlingLucas Stach1-3/+30
Commit cc7b0d495589 ("PCI: designware: Update PCI config space remap function") made PCI configuration requests non-posted, which means we now get a synchronous abort when the CFG space read to probe for downstream devices times out. Synchronous aborts need to be handled differently from the async aborts we were getting before, in particular the PC needs to be advanced when resolving the abort. This is mostly a copy of what other PCI drivers do on ARM to handle those aborts. [bhelgaas: changelog, "Fixes"] Fixes: cc7b0d495589 ("PCI: designware: Update PCI config space remap function") Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2017-05-09Merge tag 'pci-v4.12-changes' of ↵Linus Torvalds17-179/+1177
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add framework for supporting PCIe devices in Endpoint mode (Kishon Vijay Abraham I) - use non-postable PCI config space mappings when possible (Lorenzo Pieralisi) - clean up and unify mmap of PCI BARs (David Woodhouse) - export and unify Function Level Reset support (Christoph Hellwig) - avoid FLR for Intel 82579 NICs (Sasha Neftin) - add pci_request_irq() and pci_free_irq() helpers (Christoph Hellwig) - short-circuit config access failures for disconnected devices (Keith Busch) - remove D3 sleep delay when possible (Adrian Hunter) - freeze PME scan before suspending devices (Lukas Wunner) - stop disabling MSI/MSI-X in pci_device_shutdown() (Prarit Bhargava) - disable boot interrupt quirk for ASUS M2N-LR (Stefan Assmann) - add arch-specific alignment control to improve device passthrough by avoiding multiple BARs in a page (Yongji Xie) - add sysfs sriov_drivers_autoprobe to control VF driver binding (Bodong Wang) - allow slots below PCI-to-PCIe "reverse bridges" (Bjorn Helgaas) - fix crashes when unbinding host controllers that don't support removal (Brian Norris) - add driver for MicroSemi Switchtec management interface (Logan Gunthorpe) - add driver for Faraday Technology FTPCI100 host bridge (Linus Walleij) - add i.MX7D support (Andrey Smirnov) - use generic MSI support for Aardvark (Thomas Petazzoni) - make Rockchip driver modular (Brian Norris) - advertise 128-byte Read Completion Boundary support for Rockchip (Shawn Lin) - advertise PCI_EXP_LNKSTA_SLC for Rockchip root port (Shawn Lin) - convert atomic_t to refcount_t in HV driver (Elena Reshetova) - add CPU IRQ affinity in HV driver (K. Y. Srinivasan) - fix PCI bus removal in HV driver (Long Li) - add support for ThunderX2 DMA alias topology (Jayachandran C) - add ThunderX pass2.x 2nd node MCFG quirk (Tomasz Nowicki) - add ITE 8893 bridge DMA alias quirk (Jarod Wilson) - restrict Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices (Manish Jaggi) * tag 'pci-v4.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (146 commits) PCI: Don't allow unbinding host controllers that aren't prepared ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP MAINTAINERS: Add PCI Endpoint maintainer Documentation: PCI: Add userguide for PCI endpoint test function tools: PCI: Add sample test script to invoke pcitest tools: PCI: Add a userspace tool to test PCI endpoint Documentation: misc-devices: Add Documentation for pci-endpoint-test driver misc: Add host side PCI driver for PCI test function device PCI: Add device IDs for DRA74x and DRA72x dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access PCI: dwc: dra7xx: Workaround for errata id i870 dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode PCI: dwc: dra7xx: Add EP mode support PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently dt-bindings: PCI: Add DT bindings for PCI designware EP mode PCI: dwc: designware: Add EP mode support Documentation: PCI: Add binding documentation for pci-test endpoint function ixgbe: Use pcie_flr() instead of duplicating it IB/hfi1: Use pcie_flr() instead of duplicating it PCI: imx6: Fix spelling mistake: "contol" -> "control" ...
2017-04-28PCI: Don't allow unbinding host controllers that aren't preparedBrian Norris7-0/+8
Many PCI host controller drivers aren't prepared to have their devices unbound from them forcefully (e.g., through /sys/.../<driver>/unbind), as they don't provide any driver .remove callback, where they'd detach the root bus, release resources, etc. Keeping the driver built in (i.e., not a loadable module) is not enough; and providing no .remove callback just means we don't do any teardown. To rule out the possibility of unbinding a device via sysfs, we need to set the ".suppress_bind_attrs" field. I found the suspect drivers via the following search: git grep -l platform_driver $(git grep -L -e '\.remove' -e suppress_bind_attrs drivers/pci/) Then I inspected them to ensure that (a) they set up a PCI bus in their probe() and (b) they don't have a remove() callback for undoing the setup Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-28Merge branch 'pci/ioremap' into nextBjorn Helgaas7-14/+15
* pci/ioremap: PCI: versatile: Update PCI config space remap function PCI: keystone-dw: Update PCI config space remap function PCI: layerscape: Update PCI config space remap function PCI: hisi: Update PCI config space remap function PCI: tegra: Update PCI config space remap function PCI: xgene: Update PCI config space remap function PCI: armada8k: Update PCI config space remap function PCI: designware: Update PCI config space remap function PCI: iproc-platform: Update PCI config space remap function PCI: qcom: Update PCI config space remap function PCI: rockchip: Update PCI config space remap function PCI: spear13xx: Update PCI config space remap function PCI: xilinx-nwl: Update PCI config space remap function PCI: xilinx: Update PCI config space remap function PCI: ECAM: Map config region with pci_remap_cfgspace() PCI: Implement devm_pci_remap_cfgspace() devres: fix devm_ioremap_*() offset parameter kerneldoc description ARM: Implement pci_remap_cfgspace() interface ARM64: Implement pci_remap_cfgspace() interface linux/io.h: Add pci_remap_cfgspace() interface PCI: Remove __weak tag from pci_remap_iospace()
2017-04-28Merge branch 'pci/host-imx6' into nextBjorn Helgaas1-54/+144
* pci/host-imx6: PCI: imx6: Fix spelling mistake: "contol" -> "control" PCI: imx6: Do not switch speed if Gen2 is disabled PCI: imx6: Do not wait for speed change on i.MX7 PCI: imx6: Allow probe deferral by reset GPIO PCI: imx6: Add code to support i.MX7D
2017-04-28PCI: dwc: dra7xx: Workaround for errata id i870Kishon Vijay Abraham I1-0/+49
According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-28PCI: dwc: dra7xx: Add EP mode supportKishon Vijay Abraham I4-18/+221
The PCIe controller integrated in dra7xx SoCs is capable of operating in endpoint mode. Add endpoint mode support to dra7xx driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-28PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled ↵Kishon Vijay Abraham I1-6/+18
independently No functional change. Split dra7xx_pcie_enable_interrupts() into dra7xx_pcie_enable_wrapper_interrupts() and dra7xx_pcie_enable_msi_interrupts() so that wrapper interrupts and MSI interrupts can be enabled independently. This is in preparation for adding EP mode support to dra7xx driver since EP mode doesn't have to enable msi_interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-28PCI: dwc: designware: Add EP mode supportKishon Vijay Abraham I5-0/+578
Add endpoint mode support to designware driver. This uses the EP Core layer introduced recently to add endpoint mode support. *Any* function driver can now use this designware device in order to achieve the EP functionality. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-25PCI: imx6: Fix spelling mistake: "contol" -> "control"Colin Ian King1-2/+2
Trivial fix to spelling mistake in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.Zhu@nxp.com>
2017-04-24PCI: keystone-dw: Update PCI config space remap functionLorenzo Pieralisi1-1/+1
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
2017-04-24PCI: layerscape: Update PCI config space remap functionLorenzo Pieralisi1-1/+1
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
2017-04-24PCI: hisi: Update PCI config space remap functionLorenzo Pieralisi1-4/+3
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
2017-04-24PCI: armada8k: Update PCI config space remap functionLorenzo Pieralisi1-1/+1
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-04-24PCI: designware: Update PCI config space remap functionLorenzo Pieralisi1-5/+7
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-04-24PCI: qcom: Update PCI config space remap functionLorenzo Pieralisi1-1/+1
PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-04-24PCI: spear13xx: Update PCI config space remap functionLorenzo Pieralisi1-1/+1
PCI configuration space should be mapped with a memory region type that generate on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
2017-04-12PCI: hisi: Fix DT binding (hisi-pcie-almost-ecam)Dongdong Liu1-1/+5
The "hisilicon,pcie-almost-ecam" binding goes against the usual DT conventions, and is non-sensical in that it describes the IP based on what it isn't. Fix the DT binding with "hisilicon,hip06-pcie-ecam" and "hisilicon,hip07-pcie-ecam". Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-05PCI: imx6: Do not switch speed if Gen2 is disabledAndrey Smirnov1-26/+26
Save a bit of time and avoid going through link speed change procedure in configuration where link max speed is limited to Gen1 in DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
2017-04-05PCI: imx6: Do not wait for speed change on i.MX7Andrey Smirnov1-4/+15
As can be seen from [1]: "...the different behavior between iMX6Q PCIe and iMX7D PCIe maybe caused by the different controller version. Regarding to the DOC description, the DIRECT_SPEED_CHANGE should be cleared after the speed change from GEN1 to GEN2. Unfortunately, when GEN1 device is used, the behavior is not documented. So, IC design guys run the simulation and find out the following behaviors: 1. DIRECT_SPEED_CHANGE will be cleared in 7D after speed change from GEN1 to GEN2. This matches doc’s description 2. set MAX link speed(PCIE_CAP_TARGET_LINK_SPEED=0x01) as GEN1 and re-run the simulation, DIRECT_SPEED_CHANGE will not be cleared; remain as 1, this matches your result, but function test is passed, so this bit should not affect the normal PCIe function." imx6_pcie_wait_for_speed_change() will report false failures for Gen1 -> Gen1 speed transition, so avoid doing that check and just rely on imx6_pcie_wait_for_link() only. [1] https://community.nxp.com/message/867943 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
2017-04-05PCI: imx6: Allow probe deferral by reset GPIOAndrey Smirnov1-8/+17
Some designs implement reset GPIO via a GPIO expander connected to a peripheral bus. One such example would be i.MX7 Sabre board where said GPIO is provided by SPI shift register connected to a bitbanged SPI bus. To support such designs, allow reset GPIO request to defer probing of the driver. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
2017-04-05PCI: imx6: Add code to support i.MX7DAndrey Smirnov1-25/+95
Add various bits of code needed to support i.MX7D variant of the IP. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Cc: yurovsky@gmail.com Cc: Mark Rutland <mark.rutland@arm.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org
2017-04-04PCI: dwc: dra7xx: Push request_irq() call to the bottom of probeKeerthy1-7/+7
Currently devm_request_irq() is being called before base, PCI fields of dra7xx_pcie structure are populated. It is called even before pm_runtime_enable() and pm_runtime_get_sync() are called. This will lead to exceptions if in case an interrupt is triggered before the all of the above are done. Hence push the devm_request_irq() call to the end of the probe. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-04PCI: dwc: designware: Move _unroll configurations to a separate functionKishon Vijay Abraham I1-39/+58
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-04PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytesKishon Vijay Abraham I3-26/+42
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-04-04PCI: dwc: all: Modify dbi accessors to take dbi_base as argumentKishon Vijay Abraham I3-14/+29
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-04-04PCI: dwc: artpec6: Populate cpu_addr_fixup opsKishon Vijay Abraham I1-5/+6
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
2017-04-04PCI: dwc: dra7xx: Populate cpu_addr_fixup opsKishon Vijay Abraham I1-5/+6
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
2017-04-04PCI: dwc: designware: Add new *ops* for CPU addr fixupKishon Vijay Abraham I2-0/+4
Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
2017-04-04PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()Dan Carpenter1-3/+4
The bug is that "val" is unsigned long but we only initialize 32 bits of it. Then we test "if (val)" and that might be true not because we set the bits but because some were never initialized. Fixes: f342d940ee0e ("PCI: exynos: Add support for MSI") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-04PCI: dwc: Unindent dw_handle_msi_irq() loopBjorn Helgaas1-11/+11
Use "continue" to skip rest of the loop when possible to save an indent level. No functional change intended. Suggested-by: walter harms <wharms@bfs.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-04PCI: dwc: Fix dw_pcie_ops NULL pointer dereferenceNiklas Cassel2-0/+8
Fix a crash from dereferencing a NULL dw_pcie_ops pointer. For example, on ARTPEC-6: Unable to handle kernel NULL pointer dereference at virtual address 00000004 pgd = c0204000 [00000004] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-next-20170321 #1 Hardware name: Axis ARTPEC-6 Platform task: db098000 task.stack: db096000 PC is at dw_pcie_writel_dbi+0x2c/0xd0 Prior to 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures"), every driver had a struct pcie_host_ops with function pointers, typically used as: if (pp->ops->readl_rc) return pp->ops->readl_rc(...); 442ec4c04d12 split struct pcie_host_ops into two pieces: struct dw_pcie_host_ops and struct dw_pcie_ops, so the above became: if (pci->ops->readl_dbi) return pci->ops->readl_dbi(...); But pcie-artpec6.c and pcie-designware-plat.c don't need the dw_pcie_ops pointers and didn't supply a pci->ops struct, which leads to NULL pointer dereferences. Supply an empty struct dw_pcie_ops to avoid the NULL pointer dereferences. [bhelgaas: changelog] Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Joao Pinto <jpinto@synopsys.com>
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