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2023-03-11PCI: loongson: Add more devices that need MRRS quirkHuacai Chen1-9/+24
[ Upstream commit c768f8c5f40fcdc6f058cc2f02592163d6c6716c ] Loongson-2K SOC and LS7A2000 chipset add new PCI IDs that need MRRS quirk. Add them. Link: https://lore.kernel.org/r/20230211023321.3530080-1-chenhuacai@loongson.cn Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-11PCI: loongson: Prevent LS7A MRRS increasesHuacai Chen1-29/+15
[ Upstream commit 8b3517f88ff2983f52698893519227c10aac90b2 ] Except for isochronous-configured devices, software may set Max_Read_Request_Size (MRRS) to any value up to 4096. If a device issues a read request with size greater than the completer's Max_Payload_Size (MPS), the completer is required to break the response into multiple completions. Instead of correctly responding with multiple completions to a large read request, some LS7A Root Ports respond with a Completer Abort. To prevent this, the MRRS must be limited to an implementation-specific value. The OS cannot detect that value, so rely on BIOS to configure MRRS before booting, and quirk the Root Ports so we never set an MRRS larger than that BIOS value for any downstream device. N.B. Hot-added devices are not configured by BIOS, and they power up with MRRS = 512 bytes, so these devices will be limited to 512 bytes. If the LS7A limit is smaller, those hot-added devices may not work correctly, but per [1], hotplug is not supported with this chipset revision. [1] https://lore.kernel.org/r/073638a7-ae68-2847-ac3d-29e5e760d6af@loongson.cn [bhelgaas: commit log] Link: https://bugzilla.kernel.org/show_bug.cgi?id=216884 Link: https://lore.kernel.org/r/20230201043018.778499-3-chenhuacai@loongson.cn Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10PCI: qcom: Fix host-init error handlingJohan Hovold1-1/+12
[ Upstream commit 997e010de9134474dbfde52be03efd7d1bce902d ] Implement the new host_deinit() callback so that the PHY is powered off and regulators and clocks are disabled also on late host-init errors. Link: https://lore.kernel.org/r/20221017114705.8277-2-johan+linaro@kernel.org Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10PCI: mt7621: Delay phy ports initializationSergio Paracuellos1-0/+2
[ Upstream commit 0cb2a8f3456ff1cc51d571e287a48e8fddc98ec2 ] Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need to delay phy port initialization after calling the mt7621_pcie_init_port() driver function to get into reliable boots for both warm and hard resets. The delay required to detect the ports seems to be in the range [75-100] milliseconds. If the ports are not detected the controller is not functional. There is no datasheet or something similar to really understand why this extra delay is needed only for these devices and it is not for most of the boards that are built on mt7621 SoC. This issue has been reported by openWRT community and the complete discussion is in [0]. The 100 milliseconds delay has been tested in all devices to validate it. Add the extra 100 milliseconds delay to fix the issue. [0]: https://github.com/openwrt/openwrt/pull/11220 Link: https://lore.kernel.org/r/20221231074041.264738-1-sergio.paracuellos@gmail.com Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31PCI: vmd: Fix secondary bus reset for Intel bridgesFrancisco Munoz1-2/+20
[ Upstream commit 0a584655ef89541dae4d48d2c523b1480ae80284 ] The reset was never applied in the current implementation because Intel Bridges owned by VMD are parentless. Internally, pci_reset_bus() applies a reset to the parent of the PCI device supplied as argument, but in this case it failed because there wasn't a parent. In more detail, this change allows the VMD driver to enumerate NVMe devices in pass-through configurations when guest reboots are performed. There was an attempted to fix this, but later we discovered that the code inside pci_reset_bus() wasn’t triggering secondary bus resets. Therefore, we updated the parameters passed to it, and now NVMe SSDs attached to VMD bridges are properly enumerated in VT-d pass-through scenarios. Link: https://lore.kernel.org/r/20221206001637.4744-1-francisco.munoz.ruiz@linux.intel.com Fixes: 6aab5622296b ("PCI: vmd: Clean up domain before enumeration") Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Nirmal Patel <nirmal.patel@linux.intel.com> Reviewed-by: Jonathan Derrick <jonathan.derrick@linux.dev> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31PCI: imx6: Initialize PHY before deasserting core resetSascha Hauer1-6/+7
[ Upstream commit ae6b9a65af480144da323436d90e149501ea8937 ] When the PHY is the reference clock provider then it must be initialized and powered on before the reset on the client is deasserted, otherwise the link will never come up. The order was changed in cf236e0c0d59. Restore the correct order to make the driver work again on boards where the PHY provides the reference clock. This also changes the order for boards where the Soc is the PHY reference clock divider, but this shouldn't do any harm. Link: https://lore.kernel.org/r/20221101095714.440001-1-s.hauer@pengutronix.de Fixes: cf236e0c0d59 ("PCI: imx6: Do not hide PHY driver callbacks and refine the error handling") Tested-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31PCI: vmd: Disable MSI remapping after suspendNirmal Patel1-0/+5
[ Upstream commit d899aa668498c07ff217b666ae9712990306e682 ] MSI remapping is disabled by VMD driver for Intel's Icelake and newer systems in order to improve performance by setting VMCONFIG_MSI_REMAP. By design VMCONFIG_MSI_REMAP register is cleared by firmware during boot. The same register gets cleared when system is put in S3 power state. VMD driver needs to set this register again in order to avoid interrupt issues with devices behind VMD if MSI remapping was disabled before. Link: https://lore.kernel.org/r/20221109142652.450998-1-nirmal.patel@linux.intel.com Fixes: ee81ee84f873 ("PCI: vmd: Disable MSI-X remapping when possible") Signed-off-by: Nirmal Patel <nirmal.patel@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Francisco Munoz <francisco.munoz.ruiz@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31PCI: dwc: Fix n_fts[] array overrunVidya Sagar1-1/+1
[ Upstream commit 66110361281b2f7da0c8bd51eaf1f152f4236035 ] commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup") incorrectly uses pci->link_gen in deriving the index to the n_fts[] array also introducing the issue of accessing beyond the boundaries of array for greater than Gen-2 speeds. This change fixes that issue. Link: https://lore.kernel.org/r/20220926111923.22487-1-vidyas@nvidia.com Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Jingoo Han <jingoohan1@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-21PCI: mt7621: Add sentinel to quirks tableJohn Thomson1-1/+2
commit 19098934f910b4d47cb30251dd39ffa57bef9523 upstream. Current driver is missing a sentinel in the struct soc_device_attribute array, which causes an oops when assessed by the soc_device_match(mt7621_pcie_quirks_match) call. This was only exposed once the CONFIG_SOC_MT7621 mt7621 soc_dev_attr was fixed to register the SOC as a device, in: commit 7c18b64bba3b ("mips: ralink: mt7621: do not use kzalloc too early") Fix it by adding the required sentinel. Link: https://lore.kernel.org/lkml/26ebbed1-0fe9-4af9-8466-65f841d0b382@app.fastmail.com Link: https://lore.kernel.org/r/20221205204645.301301-1-git@johnthomson.fastmail.com.au Fixes: b483b4e4d3f6 ("staging: mt7621-pci: add quirks for 'E2' revision using 'soc_device_attribute'") Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-11-12PCI: hv: Only reuse existing IRTE allocation for Multi-MSIDexuan Cui1-15/+75
Jeffrey added Multi-MSI support to the pci-hyperv driver by the 4 patches: 08e61e861a0e ("PCI: hv: Fix multi-MSI to allow more than one MSI vector") 455880dfe292 ("PCI: hv: Fix hv_arch_irq_unmask() for multi-MSI") b4b77778ecc5 ("PCI: hv: Reuse existing IRTE allocation in compose_msi_msg()") a2bad844a67b ("PCI: hv: Fix interrupt mapping for multi-MSI") It turns out that the third patch (b4b77778ecc5) causes a performance regression because all the interrupts now happen on 1 physical CPU (or two pCPUs, if one pCPU doesn't have enough vectors). When a guest has many PCI devices, it may suffer from soft lockups if the workload is heavy, e.g., see https://lwn.net/ml/linux-kernel/20220804025104.15673-1-decui@microsoft.com/ Commit b4b77778ecc5 itself is good. The real issue is that the hypercall in hv_irq_unmask() -> hv_arch_irq_unmask() -> hv_do_hypercall(HVCALL_RETARGET_INTERRUPT...) only changes the target virtual CPU rather than physical CPU; with b4b77778ecc5, the pCPU is determined only once in hv_compose_msi_msg() where only vCPU0 is specified; consequently the hypervisor only uses 1 target pCPU for all the interrupts. Note: before b4b77778ecc5, the pCPU is determined twice, and when the pCPU is determined the second time, the vCPU in the effective affinity mask is used (i.e., it isn't always vCPU0), so the hypervisor chooses different pCPU for each interrupt. The hypercall will be fixed in future to update the pCPU as well, but that will take quite a while, so let's restore the old behavior in hv_compose_msi_msg(), i.e., don't reuse the existing IRTE allocation for single-MSI and MSI-X; for multi-MSI, we choose the vCPU in a round-robin manner for each PCI device, so the interrupts of different devices can happen on different pCPUs, though the interrupts of each device happen on some single pCPU. The hypercall fix may not be backported to all old versions of Hyper-V, so we want to have this guest side change forever (or at least till we're sure the old affected versions of Hyper-V are no longer supported). Fixes: b4b77778ecc5 ("PCI: hv: Reuse existing IRTE allocation in compose_msi_msg()") Co-developed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Co-developed-by: Carl Vanderlip <quic_carlv@quicinc.com> Signed-off-by: Carl Vanderlip <quic_carlv@quicinc.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/20221104222953.11356-1-decui@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2022-11-03PCI: hv: Fix the definition of vector in hv_compose_msi_msg()Dexuan Cui1-6/+16
The local variable 'vector' must be u32 rather than u8: see the struct hv_msi_desc3. 'vector_count' should be u16 rather than u8: see struct hv_msi_desc, hv_msi_desc2 and hv_msi_desc3. Fixes: a2bad844a67b ("PCI: hv: Fix interrupt mapping for multi-MSI") Signed-off-by: Dexuan Cui <decui@microsoft.com> Cc: Jeffrey Hugo <quic_jhugo@quicinc.com> Cc: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20221027205256.17678-1-decui@microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2022-10-17Revert "PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro"Jon Hunter1-3/+8
This reverts commit 8bb7ff12a91429eb76e093b517ae810b146448fe. Commit 8bb7ff12a914 ("PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro") updated the Tegra PCI driver to use the macro PCI_CONF1_EXT_ADDRESS() instead of a local function in the Tegra PCI driver. This broke PCI for some Tegra platforms because, when calculating the offset value, the mask applied to the lower 8-bits changed from 0xff to 0xfc. For now, fix this by reverting this commit. Fixes: 8bb7ff12a914 ("PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro") Link: https://lore.kernel.org/r/20221017084006.11770-1-jonathanh@nvidia.com Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-11Merge tag 'pci-v6.1-changes' of ↵Linus Torvalds13-186/+244
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Resource management: - Distribute spare resources to unconfigured hotplug bridges at boot-time (not just when hot-adding such a bridge), which makes hot-adding devices to docks work better. - Revert to a BAR assignment inherited from firmware only when the address is actually reachable via any upstream bridges, which fixes some cases where firmware doesn't configure all devices. - Add a sysfs interface to resize BARs so this can be done before assigning devices to a VM through VFIO. Power management: - Disable Precision Time Management for all devices on suspend to enable lower-power PM state. We previously did this just for Root Ports, which isn't enough because downstream devices can still generate PTM messages, which cause errors if it's disabled in the Root Port. - Save and restore the ASPM L1 PM Substates configuration for suspend/ resume. Previously this configuration was lost, so L1.x states likely stopped working after resume. - Check whether the L1 PM Substates Capability exists. If it didn't exist, we previously read junk and tried to configure L1 Substates based on that. - Fix the LTR_L1.2_THRESHOLD computation, which previously set a threshold for entering L1.2 that was too low in some cases. - Reduce the delay after transitions to or from D3cold by using usleep_range() rather than msleep(), which often slept for ~19ms instead of the 10ms normally required. The spec says 10ms is enough, but it's possible we could trip over devices that need a little more. Error handling: - Work around a BIOS bug that caused Intel Root Ports to advertise a Root Port Programmed I/O (RP PIO) log size of zero, which caused annoying warnings and prevented the kernel from dumping log registers for DPC errors. Qualcomm PCIe controller driver: - Add support for SC8280XP and SA8540P host controllers and SM8450 endpoint controller. - Disable Master AXI clock on endpoint controllers to save power when link is idle or in L1.x. - Expose link state transition counts via debugfs to help debug issues with low-power states. - Add auto-loading module support. Synopsys DesignWare PCIe controller driver: - Remove a dependency on ZONE_DMA32 by allocating the MSI target page differently. There's more work to do related to eDMA controllers, so it's not completely settled" * tag 'pci-v6.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (71 commits) PCI: qcom-ep: Check platform_get_resource_byname() return value PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Define clocks per platform PCI: qcom-ep: Make PERST separation optional dt-bindings: PCI: qcom-ep: Make PERST separation optional PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic PCI: Expose PCIe Resizable BAR support via sysfs PCI/ASPM: Correct LTR_L1.2_THRESHOLD computation PCI/ASPM: Ignore L1 PM Substates if device lacks capability PCI/ASPM: Factor out L1 PM Substates configuration PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS PCI: qcom-ep: Expose link transition counts via debugfs PCI: qcom-ep: Disable IRQs during driver remove PCI/ASPM: Save L1 PM Substates Capability for suspend/resume PCI/ASPM: Refactor L1 PM Substates Control Register programming PCI: qcom-ep: Make use of the cached dev pointer PCI: qcom-ep: Rely on the clocks supplied by devicetree PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on() ...
2022-10-06Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas3-36/+13
- Add macros for PCI Configuration Mechanism #1 and use them in the ftpci100, mt7621, and tegra drivers (Pali Rohár) * remotes/lorenzo/pci/misc: PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macro PCI: ftpci100: Use PCI_CONF1_ADDRESS() macro PCI: Add standard PCI Config Address macros
2022-10-06Merge branch 'pci/qcom'Bjorn Helgaas2-112/+180
- List platforms that use a single MSI host interrupt in qcom DT (Johan Hovold) - Add SC8280XP, SA8540P support to qcom DT binding and driver(Johan Hovold) - Make all optional clocks truly optional in the driver (Johan Hovold) - Rename per-IP structs to reflect the IP version (Johan Hovold) - Sort device ID match table by compatible string (Johan Hovold) - Add MODULE_DEVICE_TABLE to enable module autoloading (Dmitry Baryshkov) - Drop the unused .post_deinit() callback (Johan Hovold) - Rely on DT for clock information instead of hard-coding it in the driver (Manivannan Sadhasivam) - Disable IRQs when removing driver to avoid spurious IRQs later (Manivannan Sadhasivam) - Expose link transition counts via debugfs to help debug issues with low-power states (Manivannan Sadhasivam) - Gate Master AXI clock to the MHI bus while in L1 substates to save power (Manivannan Sadhasivam) - Disable Master AXI clock to save power when there is no traffic on PCIe (Manivannan Sadhasivam) - Make the "PERST separation" debug feature optional in the DT and the driver (Manivannan Sadhasivam) - Define clocks to be per-platform in DT to prepare for future SoCs (Manivannan Sadhasivam) - Add SM8450 SoC support (Manivannan Sadhasivam) - Check for platform_get_resource_byname() to avoid a NULL pointer dereference (Yang Yingliang) * pci/qcom: PCI: qcom-ep: Check platform_get_resource_byname() return value PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Define clocks per platform PCI: qcom-ep: Make PERST separation optional dt-bindings: PCI: qcom-ep: Make PERST separation optional PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS PCI: qcom-ep: Expose link transition counts via debugfs PCI: qcom-ep: Disable IRQs during driver remove PCI: qcom-ep: Make use of the cached dev pointer PCI: qcom-ep: Rely on the clocks supplied by devicetree PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure PCI: qcom: Rename host-init error label PCI: qcom: Drop unused post_deinit callback PCI: qcom-ep: Add MODULE_DEVICE_TABLE PCI: qcom: Sort device-id table PCI: qcom: Clean up IP configurations PCI: qcom: Make all optional clocks optional PCI: qcom: Add support for SA8540P PCI: qcom: Add support for SC8280XP dt-bindings: PCI: qcom: Add SA8540P to binding dt-bindings: PCI: qcom: Add SC8280XP to binding dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
2022-10-06Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas1-6/+6
- Fix endianness of emulated bridge iolimitupper, iobaseupper, memlimit and membase members (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Fix endianness when accessing PCI emul bridge members
2022-10-06Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas1-1/+1
- Rename the pcie-mediatek-gen3 driver from 'mtk-pcie' to 'mtk-pcie-gen3' so it can coexist with the pcie-mediatek driver, which also uses 'mtk-pcie' (Felix Fietkau) * remotes/lorenzo/pci/mediatek: PCI: mediatek-gen3: Change driver name to mtk-pcie-gen3
2022-10-06Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas4-29/+37
- Use dmam_alloc_coherent() instead of dma_map_page() to allocate the MSI target page, which means dwc drivers will work even when ZONE_DMA32 is disabled (Will McVicker) - If we can't allocate an MSI target page with a 32-bit address, try allocating one with a 64-bit address (Will McVicker) - Switch from of_gpio_named_count() to generic gpiod_count() (Andy Shevchenko) - Add support for i.MX8MP PCIe (Richard Zhu) - Fix the Freescale i.MX8 PHY driver, which had interchanged the phy_init() and phy_power_on() interfaces (Richard Zhu) * remotes/lorenzo/pci/dwc: phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on() PCI: imx6: Add i.MX8MP PCIe support PCI: dwc: Replace of_gpio_named_count() by gpiod_count() PCI: dwc: Drop dependency on ZONE_DMA32
2022-10-06Merge branch 'remotes/lorenzo/pci/bridge-emul'Bjorn Helgaas2-0/+2
- In an emulated PCI bridge, set Capability offsets so they match the hardware offsets shown by U-Boot (Pali Rohár) * remotes/lorenzo/pci/bridge-emul: PCI: pci-bridge-emul: Set position of PCI capabilities to real HW value
2022-10-06Merge branch 'remotes/lorenzo/pci/apple'Bjorn Helgaas1-2/+2
- Switch from gpiod_get_from_of_node() to generic devm GPIO API (Dmitry Torokhov) * remotes/lorenzo/pci/apple: PCI: apple: Do not leak reset GPIO on unbind/unload/error
2022-10-06PCI: qcom-ep: Check platform_get_resource_byname() return valueYang Yingliang1-0/+5
If platform_get_resource_byname() fails, 'mmio_res' will be set to NULL pointer, which causes a NULL pointer dereference when it is used in qcom_pcie_perst_deassert(). Check the return value to prevent it. Link: https://lore.kernel.org/r/20220429080740.1294797-1-yangyingliang@huawei.com Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
2022-10-06PCI: qcom-ep: Add support for SM8450 SoCManivannan Sadhasivam1-0/+1
Add support for SM8450 SoC to the Qualcomm PCIe Endpoint Controller driver. The driver uses the same config as the existing SDX55 chipset, so additional settings are not required. Link: https://lore.kernel.org/r/20220914075350.7992-13-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-10-06PCI: qcom-ep: Make PERST separation optionalManivannan Sadhasivam1-4/+6
PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. Make the property optional in the driver. Link: https://lore.kernel.org/r/20220914075350.7992-10-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-10-06PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe trafficManivannan Sadhasivam1-1/+8
The Master AXI clock can be disabled when it is not used i.e., when there is no traffic on the PCIe bus. This helps to save power during idle state. [bhelgaas: tidy and wrap comment] Link: https://lore.kernel.org/r/20220914075350.7992-8-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-10-05PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SSManivannan Sadhasivam1-0/+9
During L1SS, gate the Master clock supplied to the MHI bus to save power. Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-05PCI: qcom-ep: Expose link transition counts via debugfsManivannan Sadhasivam1-0/+60
Qualcomm PCIe controllers have debug registers in the MMIO region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Link: https://lore.kernel.org/r/20220914075350.7992-6-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-05PCI: qcom-ep: Disable IRQs during driver removeManivannan Sadhasivam1-6/+9
Disable the Global and PERST IRQs during driver remove to avoid getting spurious IRQs after resource deallocation. Link: https://lore.kernel.org/r/20220914075350.7992-5-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-03PCI: qcom-ep: Make use of the cached dev pointerManivannan Sadhasivam1-2/+2
In the qcom_pcie_ep_get_resources() function, dev pointer is already cached in a local variable. So let's make use of it instead of getting the dev pointer again from pdev struct. Link: https://lore.kernel.org/r/20220914075350.7992-4-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-03PCI: qcom-ep: Rely on the clocks supplied by devicetreeManivannan Sadhasivam1-20/+13
Generally, device drivers should just rely on the platform data like devicetree to supply the clocks required for the functioning of the peripheral. There is no need to hardcode the clk info in the driver. So get rid of the static clk info and obtain the platform supplied clks. The total number of clocks supplied is obtained using the devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs. Link: https://lore.kernel.org/r/20220914075350.7992-3-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-03PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structureManivannan Sadhasivam1-0/+17
Add kernel-doc for qcom_pcie_ep structure. Link: https://lore.kernel.org/r/20220914075350.7992-2-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-03phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()Richard Zhu1-3/+3
Refer to phy_core driver, phy_init() must be called before phy_power_on(). Fix the wrong order of phy_init() and phy_power_on() here. Link: https://lore.kernel.org/r/1662344583-18874-1-git-send-email-hongxing.zhu@nxp.com Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-10-03PCI: imx6: Add i.MX8MP PCIe supportRichard Zhu1-2/+25
Add i.MX8MP PCIe support. To avoid codes duplication when find the syscon regmap, add the iomux gpr syscon compatible into drvdata. Link: https://lore.kernel.org/r/1662109086-15881-8-git-send-email-hongxing.zhu@nxp.com Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-10-03PCI: dwc: Replace of_gpio_named_count() by gpiod_count()Andy Shevchenko1-2/+2
As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Link: https://lore.kernel.org/r/20220830183310.48541-1-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Rob Herring <robh@kernel.org>
2022-09-29PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-8/+3
Simplify pci-tegra.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCI config space. Link: https://lore.kernel.org/r/20220928121911.14994-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com>
2022-09-29PCI: qcom: Rename host-init error labelJohan Hovold1-2/+2
Use a more descriptive name for the reset host-init error label for consistency. Link: https://lore.kernel.org/r/20220928155421.21660-3-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-09-29PCI: qcom: Drop unused post_deinit callbackJohan Hovold1-3/+0
Drop the unused and confusingly named post_deinit callback that was added for the now removed pipe clock handling. If ever needed we can add back a callback named pre_deinit (or perhaps rather pre_phy_power_off) instead. Link: https://lore.kernel.org/r/20220928155421.21660-2-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-09-27PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-11/+6
Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCIe config space. Link: https://lore.kernel.org/r/20220924092404.31776-4-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
2022-09-27PCI: ftpci100: Use PCI_CONF1_ADDRESS() macroPali Rohár1-17/+4
Simplify pci-ftpci100.c driver code and use new PCI_CONF1_ADDRESS() macro for accessing PCI config space. Link: https://lore.kernel.org/r/20220924092404.31776-3-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-09-16PCI: aardvark: Add support for PCI Bridge Subsystem Vendor ID on emulated bridgePali Rohár1-0/+3
Register with Subsystem Device/Vendor ID is at offset 0x2c. Export it via the emulated bridge to enable support for the Subsystem Device/Vendor ID - by reading it in the PCI controller config space and storing it in the emulated bridge control structures, so that it is exposed in the respective PCI capability. After this change Subsystem ID is visible in lspci output at line: Capabilities: [40] Subsystem Link: https://lore.kernel.org/r/20220711225915.13896-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-09-14PCI: apple: Do not leak reset GPIO on unbind/unload/errorDmitry Torokhov1-2/+2
The driver allocates reset GPIO in apple_pcie_setup_port() but neither releases the resource, nor uses devm API to have it released automatically. Let's fix this by switching to devm API. While at it let's use generic devm_fwnode_gpiod_get() instead of OF-specific gpiod_get_from_of_node() - this will allow us top stop exporting the latter down the road. Link: https://lore.kernel.org/r/YxatO5OaI2RpxQ2M@google.com Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Hector Martin <marcan@marcan.st> Acked-by: Marc Zyngier <maz@kernel.org>
2022-08-30PCI: qcom-ep: Add MODULE_DEVICE_TABLEDmitry Baryshkov1-0/+1
Add MODULE_DEVICE_TABLE to enable module autoloading for respective device. Link: https://lore.kernel.org/r/20220430084740.3769925-1-dmitry.baryshkov@linaro.org Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-08-29PCI: dwc: Drop dependency on ZONE_DMA32Will McVicker2-22/+7
Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Link: https://lore.kernel.org/r/20220825235404.4132818-2-willmcvicker@google.com Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres <isaacmanjarres@google.com> Signed-off-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
2022-08-25PCI: pci-bridge-emul: Set position of PCI capabilities to real HW valuePali Rohár2-0/+2
mvebu and aardvark HW have PCIe capabilities on different offset in PCI config space. Extend pci-bridge-emul.c code to allow setting custom driver custom value where PCIe capabilities starts. With this change PCIe capabilities of both drivers are reported at the same location as where they are reported by U-Boot - in their real HW offset. Link: https://lore.kernel.org/r/20220824112124.21675-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-08-23PCI: mediatek-gen3: Change driver name to mtk-pcie-gen3Felix Fietkau1-1/+1
driver_register() will refuse to register another driver with the same name. This change allows pcie-mediatek-gen3 to coexist with pcie-mediatek built into the kernel. Link: https://lore.kernel.org/r/20220505083907.86598-1-nbd@nbd.name Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192") Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
2022-08-23PCI: mvebu: Fix endianness when accessing PCI emul bridge membersPali Rohár1-6/+6
PCI emul bridge members iolimitupper, iobaseupper, memlimit and membase are of type __le16, so correctly access these members using le16_to_cpu() macros. Link: https://lore.kernel.org/r/20220812141115.24082-1-pali@kernel.org Fixes: e7a01876729c ("PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2022-08-23PCI: qcom: Sort device-id tableJohan Hovold1-7/+7
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones. Link: https://lore.kernel.org/r/20220714071348.6792-9-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23PCI: qcom: Clean up IP configurationsJohan Hovold1-60/+29
The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks). Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs. Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp). Link: https://lore.kernel.org/r/20220714071348.6792-8-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23PCI: qcom: Make all optional clocks optionalJohan Hovold1-24/+4
The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree. This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks. Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree. Link: https://lore.kernel.org/r/20220714071348.6792-7-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23PCI: qcom: Add support for SA8540PJohan Hovold1-0/+6
The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled. Link: https://lore.kernel.org/r/20220714071348.6792-6-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-23PCI: qcom: Add support for SC8280XPJohan Hovold1-2/+20
The SC8280XP platform has seven PCIe controllers: two used with USB4, two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0 ops. Note that the SC8280XP controllers need two or three interconnect clocks to be enabled. Model these as optional clocks to avoid encoding devicetree data in the PCIe driver. Note that the same could be done for the SM8450 interconnect clocks and possibly also for the TBU clocks. Link: https://lore.kernel.org/r/20220714071348.6792-5-johan+linaro@kernel.org Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-10 20:27:31 +0300