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2011-12-03Merge branch 'master' of ↵John W. Linville21-61/+112
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless Conflicts: drivers/net/wireless/iwlwifi/iwl-agn.c drivers/net/wireless/libertas/cfg.c
2011-12-02iwlwifi: change the default behavior of watchdog timerWey-Yi Guy6-9/+26
The current default watchdog timer is enabled, but we are seeing issues on legacy devices. So change the default setting of watchdog timer to per device based. But user still can use the "wd_disable" module parameter to overwrite the system setting Cc: stable@vger.kernel.org #3.0+ Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-02iwlwifi: do not re-configure HT40 after associatedWey-Yi Guy3-28/+28
The ht40 setting should not change after association unless channel switch This fix a problem we are seeing which cause uCode assert because driver sending invalid information and make uCode confuse Here is the firmware assert message: kernel: iwlagn 0000:03:00.0: Microcode SW error detected. Restarting 0x82000000. kernel: iwlagn 0000:03:00.0: Loaded firmware version: 17.168.5.3 build 42301 kernel: iwlagn 0000:03:00.0: Start IWL Error Log Dump: kernel: iwlagn 0000:03:00.0: Status: 0x000512E4, count: 6 kernel: iwlagn 0000:03:00.0: 0x00002078 | ADVANCED_SYSASSERT kernel: iwlagn 0000:03:00.0: 0x00009514 | uPc kernel: iwlagn 0000:03:00.0: 0x00009496 | branchlink1 kernel: iwlagn 0000:03:00.0: 0x00009496 | branchlink2 kernel: iwlagn 0000:03:00.0: 0x0000D1F2 | interruptlink1 kernel: iwlagn 0000:03:00.0: 0x00000000 | interruptlink2 kernel: iwlagn 0000:03:00.0: 0x01008035 | data1 kernel: iwlagn 0000:03:00.0: 0x0000C90F | data2 kernel: iwlagn 0000:03:00.0: 0x000005A7 | line kernel: iwlagn 0000:03:00.0: 0x5080B520 | beacon time kernel: iwlagn 0000:03:00.0: 0xCC515AE0 | tsf low kernel: iwlagn 0000:03:00.0: 0x00000003 | tsf hi kernel: iwlagn 0000:03:00.0: 0x00000000 | time gp1 kernel: iwlagn 0000:03:00.0: 0x29703BF0 | time gp2 kernel: iwlagn 0000:03:00.0: 0x00000000 | time gp3 kernel: iwlagn 0000:03:00.0: 0x000111A8 | uCode version kernel: iwlagn 0000:03:00.0: 0x000000B0 | hw version kernel: iwlagn 0000:03:00.0: 0x00480303 | board version kernel: iwlagn 0000:03:00.0: 0x09E8004E | hcmd kernel: iwlagn 0000:03:00.0: CSR values: kernel: iwlagn 0000:03:00.0: (2nd byte of CSR_INT_COALESCING is CSR_INT_PERIODIC_REG) kernel: iwlagn 0000:03:00.0: CSR_HW_IF_CONFIG_REG: 0X00480303 kernel: iwlagn 0000:03:00.0: CSR_INT_COALESCING: 0X0000ff40 kernel: iwlagn 0000:03:00.0: CSR_INT: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_INT_MASK: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_FH_INT_STATUS: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_GPIO_IN: 0X00000030 kernel: iwlagn 0000:03:00.0: CSR_RESET: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_GP_CNTRL: 0X080403c5 kernel: iwlagn 0000:03:00.0: CSR_HW_REV: 0X000000b0 kernel: iwlagn 0000:03:00.0: CSR_EEPROM_REG: 0X07d60ffd kernel: iwlagn 0000:03:00.0: CSR_EEPROM_GP: 0X90000001 kernel: iwlagn 0000:03:00.0: CSR_OTP_GP_REG: 0X00030001 kernel: iwlagn 0000:03:00.0: CSR_GIO_REG: 0X00080044 kernel: iwlagn 0000:03:00.0: CSR_GP_UCODE_REG: 0X000093bb kernel: iwlagn 0000:03:00.0: CSR_GP_DRIVER_REG: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_UCODE_DRV_GP1: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_UCODE_DRV_GP2: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_LED_REG: 0X00000078 kernel: iwlagn 0000:03:00.0: CSR_DRAM_INT_TBL_REG: 0X88214dd2 kernel: iwlagn 0000:03:00.0: CSR_GIO_CHICKEN_BITS: 0X27800200 kernel: iwlagn 0000:03:00.0: CSR_ANA_PLL_CFG: 0X00000000 kernel: iwlagn 0000:03:00.0: CSR_HW_REV_WA_REG: 0X0001001a kernel: iwlagn 0000:03:00.0: CSR_DBG_HPET_MEM_REG: 0Xffff0010 kernel: iwlagn 0000:03:00.0: FH register values: kernel: iwlagn 0000:03:00.0: FH_RSCSR_CHNL0_STTS_WPTR_REG: 0X21316d00 kernel: iwlagn 0000:03:00.0: FH_RSCSR_CHNL0_RBDCB_BASE_REG: 0X021479c0 kernel: iwlagn 0000:03:00.0: FH_RSCSR_CHNL0_WPTR: 0X00000060 kernel: iwlagn 0000:03:00.0: FH_MEM_RCSR_CHNL0_CONFIG_REG: 0X80819104 kernel: iwlagn 0000:03:00.0: FH_MEM_RSSR_SHARED_CTRL_REG: 0X000000fc kernel: iwlagn 0000:03:00.0: FH_MEM_RSSR_RX_STATUS_REG: 0X07030000 kernel: iwlagn 0000:03:00.0: FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV: 0X00000000 kernel: iwlagn 0000:03:00.0: FH_TSSR_TX_STATUS_REG: 0X07ff0001 kernel: iwlagn 0000:03:00.0: FH_TSSR_TX_ERROR_REG: 0X00000000 kernel: iwlagn 0000:03:00.0: Start IWL Event Log Dump: display last 20 entries kernel: ------------[ cut here ]------------ WARNING: at net/mac80211/util.c:1208 ieee80211_reconfig+0x1f1/0x407() kernel: Hardware name: 4290W4H kernel: Pid: 1896, comm: kworker/0:0 Not tainted 3.1.0 #2 kernel: Call Trace: kernel: [<ffffffff81036558>] ? warn_slowpath_common+0x73/0x87 kernel: [<ffffffff813b8966>] ? ieee80211_reconfig+0x1f1/0x407 kernel: [<ffffffff8139e8dc>] ? ieee80211_recalc_smps_work+0x32/0x32 kernel: [<ffffffff8139e95a>] ? ieee80211_restart_work+0x7e/0x87 kernel: [<ffffffff810472fa>] ? process_one_work+0x1c8/0x2e3 kernel: [<ffffffff810480c9>] ? worker_thread+0x17a/0x23a kernel: [<ffffffff81047f4f>] ? manage_workers.clone.18+0x15b/0x15b kernel: [<ffffffff81047f4f>] ? manage_workers.clone.18+0x15b/0x15b kernel: [<ffffffff8104ba97>] ? kthread+0x7a/0x82 kernel: [<ffffffff813d21b4>] ? kernel_thread_helper+0x4/0x10 kernel: [<ffffffff8104ba1d>] ? kthread_flush_work_fn+0x11/0x11 kernel: [<ffffffff813d21b0>] ? gs_change+0xb/0xb Cc: <stable@kernel.org> 3.1+ Reported-by: Udo Steinberg <udo@hypervisor.org> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-02iwlagn: fix HW crypto for TX-only keysJohannes Berg2-5/+11
Group keys in IBSS or AP mode are not programmed into the device since we give the key to it with every TX packet. However, we do need mac80211 to create the MMIC & PN in all cases. Move the code around to set the key flags all the time. We set them even when the key is removed again but that is obviously harmless. Cc: stable@vger.kernel.org Reported-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: add default chainmask for AR9462Mohammed Shafi Shajakhan1-0/+2
the default tx/rx chainmask for AR9462 is 0x3. this patch helps to assign 0x3 rather than 0x7 for AR9462 with the help of fix_chainmask module if something goes wrong in reading tx/rx chain mask from OTP/EEPROM card(though its very unlikely) Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: Fix TX IQ calibration for AR9003Mohammed Shafi Shajakhan1-1/+1
only for AR9485 (or) later chipsets TxIQ calibration runs as part of AGC calibration. without this patch TX IQ cal completion i.e. ar9003_hw_tx_iq_cal_run won't be executed for AR9003 Reviewed-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01brcm80211: fmac: small memory leak on errorDan Carpenter1-1/+3
We should free "bus_if" here, it's a small leak but it makes the static checkers happy. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: minor cleanupMohammed Shafi Shajakhan1-1/+0
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: fix a typoMohammed Shafi Shajakhan1-1/+1
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: MCI state machine based on MCI interruptMohammed Shafi Shajakhan5-1/+359
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: Add MCI related changes in chip resetMohammed Shafi Shajakhan1-0/+132
here we check for BT state and if BT calibration has started, give 25ms for BT Calibration to finish. we also take care of 2G/5G switch and LNA transfer incase WLAN is operating in 5G. in case the BT state is awake when we do WLAN calibration re-calibrate and we reset the message exchange between WLAN and BT. BT is given preference when simultaneous CAL request happens. calibration for WLAN/BT is done assuming that the other co-existing module is in awake state, if not we continue to do calibration while if the other module's state changes we need to do restart the calibration handshake Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: Add support for MCI WLAN calibrationMohammed Shafi Shajakhan1-0/+43
WLAN communicates with BT for its calibration by sending WLAN_CAL_REQ, waits for BT_CAL_GRANT. This is done with the help of GPM messages. also WLAN_CAL_DONE messages is sent once WLAN calibration is done. Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: MCI related changes in set_reset_regMohammed Shafi Shajakhan1-3/+11
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: MCI related changes in chip managementMohammed Shafi Shajakhan2-0/+26
send halt BT GPM if the chip is in network sleep and BT state is awake Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: Add functions to allocate/free buffers for MCIMohammed Shafi Shajakhan3-0/+81
required buffers and dma allocation is done for GPM and SCHED messages Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: add MCI specific definitions and structuresMohammed Shafi Shajakhan1-0/+17
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: check for MCI interrupt in get_isrMohammed Shafi Shajakhan1-2/+34
check for the condition of MCI interrupt being triggered and appropriately obtain the values of MCI_INTERRUPT_RX_MSG_RAW and MCI_INTERRUPT_RAW Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: check for asynchronous MCI interrupt pendingMohammed Shafi Shajakhan1-1/+4
MCI interrupt is an asynchronous one, so take care of it by having a check in ath9k_hw_intrpend, which actually decides whether the interrupt is really for the driver from ath_isr Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: take care of enabling MCI interruptsMohammed Shafi Shajakhan1-4/+8
enable MCI interrupt when ath9k_hw_enable_interrupts is called, like during the completion of chip_reset before which the interrupts are disabled Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: Add MCI interrupt to interrupt maskMohammed Shafi Shajakhan1-1/+5
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: Add MCI h/w code and state machineMohammed Shafi Shajakhan3-1/+1492
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: initialize MCI parametersMohammed Shafi Shajakhan1-0/+22
these parameter will be utilized and modified in the MCI hardware codes state machine Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: Add MCI h/w specific structureMohammed Shafi Shajakhan1-0/+31
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: add GPIO output MUX related macrosMohammed Shafi Shajakhan1-0/+10
Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k_hw: add definitions to support MCI h/w codeMohammed Shafi Shajakhan4-26/+529
these definitions will be used by MCI state machine and the corresponding hardware code Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01prism54: remove private driver ioctlsLuis R. Rodriguez3-336/+0
As of hostap_0_7_1~358 the CONFIG_DRIVER_PRISM54 was removed from upstream wpa_supplicant/hostapd so lets just kill the useless old prism54 private ioctl crap. Cc: Jouni Malinen <j@w1.fi> Cc: David Miller <davem@davemloft.net> Reported-by: David Miller <davem@davemloft.net> Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: change the default antenna settings based on diversityMohammed Shafi Shajakhan1-9/+14
change the AR_DEF_ANTENNA register settings i.e setting default antenna setting only for antenna diversity enabled chipsets. no point in doing this for MIMO chipsets Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01ath9k: Fix LED GPIO pin for AR9462Mohammed Shafi Shajakhan1-1/+1
GPIO pin 4 is assigned AR9462 chipsets LED. while GPIO pin 0 worked for obselete AR9462 chipsets though they are meant for EEPROM as per Russell Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Russell Hu <rhu@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01mwifiex: fix usage of set tx powerLuis R. Rodriguez1-1/+2
mBm is passed but dBm was assumed... Acked-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01brcm80211: avoid code duplication on set tx powerLuis R. Rodriguez1-6/+0
Both cases are doing the same so treat the switch cases for both as an "or". Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-12-01brcm80211: fix usage of set tx powerLuis R. Rodriguez1-1/+2
mBm is passed but dBm was assumed... Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlwifi: help to debug AGG SM inconsistenciesEmmanuel Grumbach1-2/+10
Add more data when inconsistencies occur in the AGG state machine. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlwifi: show the configuration optionWey-Yi Guy1-0/+32
Not sure it is the best way to do it, but many times we want to know what the configuration options were enabled for the compiled driver. Let's just log the options during load time; so there were be no confusion. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlwifi: show command string for REPLY_D3_CONFIGWey-Yi Guy1-0/+1
missing the string, add it Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlagn: allow up to uCode API 6 for 6000 devicesJohannes Berg1-2/+5
Since the uCode hasn't been released (yet?), warn only if using older than API 4, but load anything up to API 6. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlagn: dynamically allocate & reflect calibration dataJohannes Berg5-73/+46
This makes handling the calibration data more generic and no longer requires updating IWL_CALIB_MAX when a new uCode comes with more calibration packets. Since we just copy the data back, there's also no need for understanding which calibration we received -- we can just reflect it back to the runtime uCode. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlagn: remove calibration knowledgeJohannes Berg8-75/+22
The init microcode knows very well which calibrations are required and sends us results for those that are. Consequently, we can just send all of those to the RT uCode again. The problem with having the driver know about this is that it is a uCode feature, not a hardware feature so the config is completely unsuitable. The only thing we need to check is whether the device needs crystal calibration or not, add a new parameter to the configuration for that. This makes new uCode work on 6000 series devices. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28iwlwifi: add tm commands for indirect register accessHsu, Kenny2-13/+47
Create new testmode commands to suppot indirect access of peripheral register. - IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32 - IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32 Meanwhile, add affix "DIRECT" into original register access commands for better discrimination with new commands. - IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32 - IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32 - IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8 Signed-off-by: Kenny Hsu <kenny.hsu@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Optimize ath5k_cw_validateNick Kossifidis1-4/+13
Optimize ath5k_cw_validate by using the classic (X & (X - 1)) == 0 check to see if a number is power of 2. v2: Use functions from log2.h instead Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Renumber hw queue idsNick Kossifidis2-13/+11
According to documentation higher DCUs have higher priority and should be used for beacons and CAB traffic. More specifically DCU 9 should be used for beacons and DCU 8 for CAB traffic, I assumed DCU 7 should be OK for UAPSD traffic. Note that DCU 8 and 9 are special because they can only be mapped to a single QCU each but since we use a 1:1 mapping between QCUs and DCUs anyway we don't have to change much. P.S. I also did a few related cleanups on qcu.c and ath5k.h Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: ath5k_ani_period_restart only touches struct ath5k_ani_stateNick Kossifidis1-4/+3
No need to take ath5k_hw as an argument. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: MRR support and 2GHz radio override belong in ah_capabilitiesNick Kossifidis5-48/+47
MRR support and 2GHz radio override belong in ah_capabilities and we should use them (e.g. so far we used to set mrr descriptor without checking if MRR support is enabled + we checked for MRR support 2 times, one by trying to set up an MRR descriptor and another one based on MAC version). Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Add a module parameter to disable hw rf kill switchNick Kossifidis1-2/+9
Add a module parameter to disable hw rf kill switch (GPIO interrupt) because in some cases when the card doesn't come with the laptop, EEPROM configuration doesn't match laptop's configuration and rf kill interrupt always fires up and disables hw. I thought of moving this to debugfs and make it per-card but this way it's easier for users and distros to handle. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Tested-by: Pavel Roskin <proski@gnu.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: We always do full calibration on AR5210Nick Kossifidis1-0/+3
There is no short calibration on AR5210, make sure we treat it always as full calibration. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Cleanups v2 + add kerneldoc on all hw functionsNick Kossifidis16-725/+1944
No functional changes Add kernel doc for all ath5k_hw_* functions and strcucts. Also do some cleanup, rename ath5k_hw_init_beacon to ath5k_hw_init_beacon_timers, remove an unused variable from ath5k_hw_pcu_init and a few obsolete macros, mostly related to XR. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Use usleep_range where possibleNick Kossifidis4-20/+20
Use usleep_range where possible to reduce busy waits Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Calibration re-workNick Kossifidis3-62/+147
Noise floor calibration does not interfere with traffic and should run more often as part of our "short calibration". The full calibration is not the noise floor calibration but the AGC + Gain_F (on RF5111 and RF5112) calibration and should run less often because it does interfere with traffic. So Short calibration -> I/Q & NF Calibration Long calibration -> Short + AGC + Gain_F This patch was for some time on my pub/ dir on www.kernel.org and has been tested by a few people and me. I think it's O.K. to go in. I also changed ah_calibration to ah_iq_cal_needed to make more sense. v2 Use a workqueue instead of a tasklet for calibration Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Cleanups v1Nick Kossifidis2-33/+96
No functional changes, just a few comments/documentation/cleanup Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Add TXNOFRM to INT_TX_ALLNick Kossifidis1-0/+1
Add TXNOFRM to INT_TX_ALL since it's a TX interrupt too. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-11-28ath5k: Switch from read-and-clear to write-to-clear method when handling ↵Nick Kossifidis4-93/+189
PISR/SISR registers Since card has 12 tx queues and we want to keep track of the interrupts per queue we can't fit all these interrupt bits on a single register. So we have 5 registers, the primary interrupt status register (PISR) and the 4 secondary interupt status registers (SISRs). In order to be able to read them all at once (atomic operation) Atheros introduced the Read-And-Clear registers to make things easier. So when reading RAC_PISR register, hw does a read on PISR and all SISRs, returns the value of PISR, copies all SISR values to their shadow copies (RAC_SISRx) and clears PISR and SISRs. This saves us from reading PISR/SISRs in a sequence. So far we 've used this approach and MadWiFi/Windows driver etc also used it for years. It turns out this operation is not atomic after all (at least not on all cards) That means it's possible to loose some interrupts because they came after the copy step and hw cleared them on the clean step ! That's probably the reason we got missed beacons, got stuck queues etc and couldn't figure out what was going on. With this patch we switch from RaC operation to an alternative method (that makes more sense IMHO anyway, I just chose to be on the safe side so far). Instead of reading RAC registers, we read the normal PISR/SISR registers and clear any bits we got by writing them back on the register. This will clear only the bits we got on our read step and leave any new bits unaffected (at least that's what docs say). So if any new interrupts come up we won't miss it. I've tested this with an AR5213 and an AR2425 and it seems O.K. Many thanks to Adrian Chadd for debuging this and reviewing the patch ! v2: Make sure we don't clear PISR bits that map to SISR generated interrupts (added a comment on the code for this) Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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