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path: root/drivers/net/ethernet/mellanox
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2018-07-24net/mlx5e: Use PARTIAL_GSO for UDP segmentationBoris Pismenny5-140/+23
This patch removes the splitting of UDP_GSO_L4 packets in the driver, and exposes UDP_GSO_L4 as a PARTIAL_GSO feature. Thus, the network stack is not responsible for splitting the packet into two. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5e: Support offloading double vlan push/pop tc actionsJianbo Liu3-20/+58
As we can configure two push/pop actions in one flow table entry, add support to offload those double vlan actions in a rule to HW. Signed-off-by: Jianbo Liu <jianbol@mellanox.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5e: Refactor tc vlan push/pop actions offloadingJianbo Liu3-28/+41
Extract actions offloading code to a new function, and also extend data structures for double vlan actions. Signed-off-by: Jianbo Liu <jianbol@mellanox.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5e: Support offloading tc double vlan headers matchJianbo Liu1-3/+52
We can match on both outer and inner vlan tags, add support for offloading that. Signed-off-by: Jianbo Liu <jianbol@mellanox.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5e: Remove redundant WARN when we cannot find neigh entryRoi Dayan1-3/+1
It is possible for neigh entry not to exist if it was cleaned already. When we bring down an interface the neigh gets deleted but it could be that our listener for neigh event to clear the encap valid bit didn't start yet and the neigh update last used work is started first. In this scenario the encap entry has valid bit set but the neigh entry doesn't exist. Signed-off-by: Roi Dayan <roid@mellanox.com> Reviewed-by: Paul Blakey <paulb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, Add debug printsSaeed Mahameed1-2/+11
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, Enable tracingFeras Daoud3-4/+18
Add the tracer file to the makefile and add the init function to the load one flow. Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, parse traces and kernel tracing supportFeras Daoud3-2/+333
For each message the driver should do the following: 1- Find the message string in the strings database 2- Count the param number of each message 3- Wait for the param events and accumulate them 4- Calculate the event timestamp using the local event timestamp and the first timestamp event following it. 5- Print message to trace log Enable the tracing by: echo 1 > /sys/kernel/debug/tracing/events/mlx5/mlx5_fw/enable Read traces by: cat /sys/kernel/debug/tracing/trace Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, events handlingFeras Daoud3-10/+340
The tracer has one event, event 0x26, with two subtypes: - Subtype 0: Ownership change - Subtype 1: Traces available An ownership change occurs in the following cases: 1- Owner releases his ownership, in this case, an event will be sent to inform others to reattempt acquire ownership. 2- Ownership was taken by a higher priority tool, in this case the owner should understand that it lost ownership, and go through tear down flow. The second subtype indicates that there are traces in the trace buffer, in this case, the driver polls the tracer buffer for new traces, parse them and prepares the messages for printing. The HW starts tracing from the first address in the tracer buffer. Driver receives an event notifying that new trace block exists. HW posts a timestamp event at the last 8B of every 256B block. Comparing the timestamp to the last handled timestamp would indicate that this is a new trace block. Once the new timestamp is detected, the entire block is considered valid. Block validation and parsing, should be done after copying the current block to a different location, in order to avoid block overwritten during processing. Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, register log buffer memory keySaeed Mahameed1-3/+61
Create a memory key and protection domain for the tracer log buffer. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, create trace buffer and copy strings databaseFeras Daoud2-3/+224
For each PF do the following: 1- Allocate memory for the tracer strings database and read the strings from the FW to the SW. These strings will be used later for parsing traces. 2- Allocate and dma map tracer buffers. Traces that will be written into the buffer will be parsed as a group of one or more traces, referred to as trace message. The trace message represents a C-like printf string. First trace of a message holds the pointer to the correct string in strings database. The following traces holds the variables of the message. Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24net/mlx5: FW tracer, implement tracer logicFeras Daoud2-0/+262
Implement FW tracer logic and registers access, initialization and cleanup flows. Initializing the tracer will be part of load one flow, as multiple PFs will try to acquire ownership but only one will succeed and will be the tracer owner. Signed-off-by: Feras Daoud <ferasda@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-24Merge branch 'mlx5-next' of ↵Saeed Mahameed10-72/+60
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux mlx5 core infrastructure updates and fixes. From Eran: - Add MPEGC (Management PCIe General Configuration) registers and btis - Fix tristate and description for MLX5 module rom Feras: - Add hardware structures for the firmware tracer From Jainbo: - Core support for double vlan push/pop steering action From Max: - Add XRQ commands definitions From Noa: - Add missing SET_DRIVER_VERSION command translation From Roi: - Use ERR_CAST() instead of coding it From Tariq: - Better return types for CQE API Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-21Merge ra.kernel.org:/pub/scm/linux/kernel/git/torvalds/linuxDavid S. Miller2-26/+30
All conflicts were trivial overlapping changes, so reasonably easy to resolve. Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-19net/mlx5: Fix tristate and description for MLX5 moduleEran Ben Elisha2-4/+4
Current description did not include new devices. Fix that by proving the correct generic description. Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-19net/mlx5: Use ERR_CAST() instead of coding itRoi Dayan1-1/+1
This makes it more readable that rule is being used to return an err. Signed-off-by: Roi Dayan <roid@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-19net/mlx5: Add missing SET_DRIVER_VERSION command translationNoa Osherovich1-0/+1
When translating command opcodes to a string, SET_DRIVER_VERSION command was missing. Fixes: 42ca502e179d0 ('net/mlx5_core: Use a macro in mlx5_command_str()') Signed-off-by: Noa Osherovich <noaos@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-19net/mlx5: Add XRQ commands definitionsMax Gurtovoy1-0/+8
Update mlx5 command list and error return function to handle XRQ commands. Signed-off-by: Max Gurtovoy <maxg@mellanox.com> Reviewed-by: Daniel Jurgens <danielj@mellanox.com> Reviewed-by: Artemy Kovalyov <artemyko@mellanox.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-19net/mlx5: Add core support for double vlan push/pop steering actionJianbo Liu4-7/+17
As newer firmware supports double push/pop in a single FTE, we add core bits and extend vlan action logic for it. Signed-off-by: Jianbo Liu <jianbol@mellanox.com> Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2018-07-18net/mlx5: fix an unused-function warningArnd Bergmann1-1/+1
These dummy helpers are all intended to be inline functions, but one of them by accident came without the 'inline' keyword, causing a harmless warning: In file included from drivers/net/ethernet/mellanox/mlx5/core/main.c:63: drivers/net/ethernet/mellanox/mlx5/core/accel/tls.h:79:1: error: 'mlx5_accel_tls_add_flow' defined but not used [-Werror=unused-function] mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow, Fixes: ab412e1dd7db ("net/mlx5: Accel, add TLS rx offload routines") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum: Extend to support Spectrum-2 ASICJiri Pirko2-32/+139
Extend existing driver for Spectrum ASIC to support Spectrum-2 ASIC. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum_acl: Add initial Spectrum-2 ACL implementationJiri Pirko7-1/+334
Utilize only C-TCAM for now. Do very minimal A-TCAM initialization in order to make C-TCAM work. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum_acl: Add region association callbackIdo Schimmel3-0/+15
In Spectrum-2, ACL regions that use 8 or 12 key blocks require several consecutive hardware regions. In order to allow defragmentation, the device stores a mapping from a logical region ID to an hardware region ID, which is similar to the page table that is used to translate virtual addresses to physical addresses. Add the region association callback to the region create sequence and implement it as a NOP in Spectrum which does not require it. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum_acl: Add support for Spectrum-2 block encodingIdo Schimmel1-0/+68
Encode each flexible key block in the general block scheme according its block index. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum_acl: Prepare for Spectrum-2 block encodingIdo Schimmel3-53/+66
In Spectrum the key (and mask) block layout is very straight forward and every block is 16 bytes aligned. However, in Spectrum-2 the blocks are not even byte aligned, which makes it difficult to encode them using current method. Instead, first encode each block and then encode the block in the general blocks layout. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add Policy-Engine General Configuration RegisterIdo Schimmel1-0/+23
The PGCR register configures general Policy-Engine settings. Specifically, we are going to use it in order to set the default action base pointer, which determines where the default action (when there is no hit) is located for each region. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add Policy-Engine Region eRP RegisterIdo Schimmel1-0/+71
The PERERP register configures the region eRPs. It can be used, for example, to enable lookup in the C-TCAM in addition to the A-TCAM. To be able to perform a lookup in the C-TCAM we need to "use" the eRP table. This is done by marking the pointer as valid, but zeroing the eRP table vector. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add Policy-Engine Region Configuration RegisterIdo Schimmel1-0/+57
The PERCR register configures the region parameters such as whether to consult the bloom filter before performing a lookup using a specific eRP. For C-TCAM only usage we don't need to accurately set the master mask. Instead, we can set all of its bits to make sure all the extracted keys are actually used. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add Policy-Engine Region Association RegisterJiri Pirko1-0/+43
The PERAR register is used to associate a hw region for region_id's. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: acl: Introduce activity get operation for action block/setJiri Pirko3-0/+35
In Spectrum-2, activity cannot be find out by TCAM rule (PTCEv2 register), but rather by associated action set. For that purpose, extend action ops to allow query activity from PEFA register. Block activity is decided according to activity of the first set. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add support for activity information from PEFA registerJiri Pirko2-6/+45
In Spectrum-2, the PEFA register is extend to report if the action set was hit during processing of packets. Introduce this extension and adjust the code around this accordingly. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum: Introduce flex key blocks for Spectrum-2Jiri Pirko2-0/+111
Introduce key blocks for Spectrum-2 that contains the same elements used already for Spectrum1. Along with that, introduce encoder stub. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum: Add Spectrum-2 variant of flex actions opsJiri Pirko2-0/+13
In Spectrum-2, no action set is stored directly in TCAM, all are located in KVD linear. So ask core to treat the first set as dummy empty one, to be just used for PTCEV2 purposes. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum_mr_tcam: Add Spectrum-2 stubsJiri Pirko3-1/+86
Add dummy ops for now. The ops are going to be implemented later on. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: spectrum: Add KVDL manager implementation for Spectrum-2Jiri Pirko3-1/+307
In Spectrum-2, KVD linear indexes are hashed into KVD hash. Therefore it is possible for multiple resource types to use same indexes. There are multiple index spaces. Also, the index space is bigger than the actual KVD hash area, which allows to have holes in the index space without any penalization. The HW has to be told in case the index for particular resource type is no longer used so it can be freed from KVD hash. IEDR register is used for that. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-18mlxsw: reg: Add Infrastructure Entry Delete RegisterJiri Pirko1-0/+62
The IEDR register is used for deleting entries from the entry tables. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-17net/mlx4_en: Don't reuse RX page when XDP is setSaeed Mahameed1-2/+6
When a new rx packet arrives, the rx path will decide whether to reuse the remainder of the page or not according to one of the below conditions: 1. frag_info->frag_stride == PAGE_SIZE / 2 2. frags->page_offset + frag_info->frag_size > PAGE_SIZE; The first condition is no met for when XDP is set. For XDP, page_offset is always set to priv->rx_headroom which is XDP_PACKET_HEADROOM and frag_info->frag_size is around mtu size + some padding, still the 2nd release condition will hold since XDP_PACKET_HEADROOM + 1536 < PAGE_SIZE, as a result the page will not be released and will be _wrongly_ reused for next free rx descriptor. In XDP there is an assumption to have a page per packet and reuse can break such assumption and might cause packet data corruptions. Fix this by adding an extra condition (!priv->rx_headroom) to the 2nd case to avoid page reuse when XDP is set, since rx_headroom is set to 0 for non XDP setup and set to XDP_PACKET_HEADROOM for XDP setup. No additional cache line is required for the new condition. Fixes: 34db548bfb95 ("mlx4: add page recycling in receive path") Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Suggested-by: Martin KaFai Lau <kafai@fb.com> CC: Eric Dumazet <edumazet@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-17mlxsw: spectrum: Expose counters for various packet sizesJiri Pirko2-1/+124
Expose counters ASIC has in the group of RFC 2819 counters that count number of packets within specific size range. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: IPsec, fix byte count in CQEBoris Pismenny3-2/+3
This patch fixes the byte count indication in CQE for processed IPsec packets that contain a metadata header. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5: Accel, add common metadata functionsBoris Pismenny3-29/+45
This patch adds common functions to handle mellanox metadata headers. These functions are used by IPsec and TLS to process FPGA metadata. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: TLS, build TLS netdev from capabilitiesBoris Pismenny1-2/+16
This patch enables TLS Rx based on available HW capabilities. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: TLS, add software statisticsBoris Pismenny3-1/+17
This patch adds software statistics for TLS to count important events. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: TLS, add Innova TLS rx data pathBoris Pismenny3-3/+118
Implement the TLS rx offload data path according to the requirements of the TLS generic NIC offload infrastructure. Special metadata ethertype is used to pass information to the hardware. When hardware loses synchronization a special resync request metadata message is used to request resync. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: Ilya Lesokhin <ilyal@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: TLS, add innova rx supportBoris Pismenny2-15/+46
Add the mlx5 implementation of the TLS Rx routines to add/del TLS contexts, also add the tls_dev_resync_rx routine to work with the TLS inline Rx crypto offload infrastructure. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: Ilya Lesokhin <ilyal@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5: Accel, add TLS rx offload routinesBoris Pismenny4-46/+134
In Innova TLS, TLS contexts are added or deleted via a command message over the SBU connection. The HW then sends a response message over the same connection. Complete the implementation for Innova TLS (FPGA-based) hardware by adding support for rx inline crypto offload. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: Ilya Lesokhin <ilyal@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16net/mlx5e: TLS, refactor variable namesBoris Pismenny3-8/+8
For symmetry, we rename mlx5e_tls_offload_context to mlx5e_tls_offload_context_tx before we add mlx5e_tls_offload_context_rx. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Reviewed-by: Aviad Yehezkel <aviadye@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-16tls: Refactor tls_offload variable namesBoris Pismenny1-3/+3
For symmetry, we rename tls_offload_context to tls_offload_context_tx before we add tls_offload_context_rx. Signed-off-by: Boris Pismenny <borisp@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-15Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextDavid S. Miller2-2/+0
Daniel Borkmann says: ==================== pull-request: bpf-next 2018-07-15 The following pull-request contains BPF updates for your *net-next* tree. The main changes are: 1) Various different arm32 JIT improvements in order to optimize code emission and make the JIT code itself more robust, from Russell. 2) Support simultaneous driver and offloaded XDP in order to allow for advanced use-cases where some work is offloaded to the NIC and some to the host. Also add ability for bpftool to load programs and maps beyond just the cgroup case, from Jakub. 3) Add BPF JIT support in nfp for multiplication as well as division. For the latter in particular, it uses the reciprocal algorithm to emulate it, from Jiong. 4) Add BTF pretty print functionality to bpftool in plain and JSON output format, from Okash. 5) Add build and installation to the BPF helper man page into bpftool, from Quentin. 6) Add a TCP BPF callback for listening sockets which is triggered right after the socket transitions to TCP_LISTEN state, from Andrey. 7) Add a new cgroup tree command to bpftool which iterates over the whole cgroup tree and prints all attached programs, from Roman. 8) Improve xdp_redirect_cpu sample to support parsing of double VLAN tagged packets, from Jesper. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-14mlxsw: spectrum_router: Optimize processing of VRRP MACsIdo Schimmel2-0/+66
Hosts using a VRRP router send their packets with a destination MAC of the VRRP router which is of the following form [1]: IPv4 - 00-00-5E-00-01-{VRID} IPv6 - 00-00-5E-00-02-{VRID} Where VRID is the ID of the virtual router. Such packets are directed to the router block in the ASIC by an FDB entry that was added in the previous patch. However, in certain cases it is possible to skip this FDB lookup and send such packets directly to the router. This is accomplished by adding these special MAC addresses to the RIF cache. If the cache is hit, the packet will skip the L2 lookup and ingress the router with the RIF specified in the cache entry. 1. https://tools.ietf.org/html/rfc5798#section-7.3 Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-14mlxsw: spectrum: Add VRRP trapsIdo Schimmel2-0/+4
Virtual Router Redundancy Protocol packets are used to communicate the state of the Master router associated with the virtual router ID (VRID). These are link-local multicast packets sent with IP protocol 112 that are trapped in the router block in the ASIC. Add a trap for these packets and mark the trapped packets to prevent them from potentially being re-flooded by the bridge driver. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>