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2020-05-11mtd: rawnand: Add a helper to check supported operationsMiquel Raynal1-0/+9
Let's use a helper to clearly check if an operation is supported or not. Return -ENOTSUPP when ->exec_op() is not implemented as we cannot know. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-8-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Avoid indirect access to ->data_buf()Miquel Raynal1-1/+1
The logic in nand_do_read_ops() is to use a bufpoi variable, either set to the original buffer, or set to a bounce buffer which in the end happens to be chip->data_buf depending on the value of the use_bounce_buf boolean. This is not a reason to call chip->data_buf directly when we know that we are using the bounce buffer. Let's use bufpoi instead to be consistent. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-7-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Rename the use_bufpoi variablesMiquel Raynal1-17/+17
Both in nand_do_read_ops() and nand_do_write_ops() there is a boolean called use_bufpoi which is set to true in case of unaligned request or when there is a need for a DMA-able buffer. It basically means "use a bounce buffer". Depending on the value of use_bufpoi, the bufpoi variable is always used and will either point to the original buffer or to the nand_chip structure "internal data buffer" (this buffer is allocated with kmalloc() on purpose so that it will be DMA-compliant). In all cases bufpoi is used so the boolean name is misleading. Rename use_bufpoi to be use_bouce_buf to be more accurate. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-6-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Fix comments about the use of bufpoiMiquel Raynal1-2/+8
Clarify these comments which are not very accurate (even wrong in the read case). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-5-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Rename a NAND chip optionMiquel Raynal11-12/+12
NAND controller drivers can set the NAND_USE_BOUNCE_BUFFER flag to a chip 'option' field. With this flag, the core is responsible of providing DMA-able buffers. The current behavior is to not force the use of a bounce buffer when the core thinks this is not needed. So in the end the name is a bit misleading, because in theory we will always have a DMA buffer but in practice it will not always be a bounce buffer. Rename this flag NAND_USES_DMA to be more accurate. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-4-miquel.raynal@bootlin.com
2020-05-11ubi: Relax the 'no MLC' rule and allow MLCs operating in SLC modeBoris Brezillon1-1/+4
The MTD layer provides an SLC mode (purely software emulation of SLC behavior) addressing the paired-pages corruption issue, which was the main reason for refusing attaching MLC NANDs to UBI. Relax this rule and allow partitions that have the MTD_EMULATE_SLC_ON_MLC flag set to be attached. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Richard Weinberger <richard@nod.at> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-9-miquel.raynal@bootlin.com
2020-05-11mtd: cmdlinepart: Add an slc option to use SLC mode on a partBoris Brezillon1-2/+10
Add a new option to set the MTD_SLC_ON_MLC_EMULATION flag. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-8-miquel.raynal@bootlin.com
2020-05-11mtd: partitions: ofpart: Parse the slc-mode propertyBoris Brezillon1-0/+3
Parse the slc-mode property and set the MTD_MLC_IN_SLC_MODE flag when present. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-7-miquel.raynal@bootlin.com
2020-05-11mtd: Add support for emulated SLC mode on MLC NANDsBoris Brezillon2-39/+204
MLC NANDs can be made a bit more reliable if we only program the lower page of each pair. At least, this solves the paired-pages corruption issue. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-5-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: toshiba: Set the pairing scheme for TC58TEG5DCLTA00Boris Brezillon1-0/+3
TC58TEG5DCLTA00 uses a stride of 3 between its lower and upper page. Set the appropriate pairing scheme at init time. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-4-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Define the "distance 3" MLC pairing schemeBoris Brezillon2-0/+53
Define a new page pairing scheme for MLC NANDs with a distance of 3 pages between the lower and upper page. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-3-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: toshiba: Add a specific init for TC58TEG5DCLTA00Boris Brezillon1-0/+11
TC58TEG5DCLTA00 is an MLC NAND which requires scrambling and supports SDR timings mode 5. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200503155341.16712-2-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: cs553x: Get rid of the legacy interface implementationBoris Brezillon1-72/+0
Now that exec_op() is implemented we no longer need to implement the legacy hooks. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501090650.1138200-5-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: cs553x: Implement exec_op()Boris Brezillon1-1/+125
So we can later get rid of the legacy hooks. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501090650.1138200-4-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: cs553x: Stop using chip->legacy.IO_ADDR_{R, W}Boris Brezillon1-23/+34
Now that we have our own controller struct we can keep the MMIO pointer in there and use instead of using the chip->legacy.IO_ADDR_{R,W} fields. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501090650.1138200-3-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: cs553x: Declare controllers instead of NAND chipsBoris Brezillon1-11/+22
The CS553x companion chip embeds 4 NAND controllers. Declare them as NAND controllers instead of NAND chips. That's done in preparation of the transition to exec_op(). Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501090650.1138200-2-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: jedec: Use intermediate variables to improve readabilityMiquel Raynal1-2/+3
Before reworking a little bit the JEDEC detection code, let's clean the coding style of an if statement to improve readability. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-10-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: jedec: Define the number of parameter pagesMiquel Raynal1-2/+4
Use a macro to define the number of parameter page instead of hardcoding it everywhere. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-9-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Drop a useless parameter page readMiquel Raynal1-6/+4
During detection the logic on the NAND bus is: /* Regular ONFI detection */ 1/ read the three NAND parameter pages /* Extended parameter page detection */ 2/ send "read the NAND parameter page" commands without reading actual data 3/ move the column pointer to the extended page and read it If fact, as long as there is nothing happening on the NAND bus between 1/ and 3/, the operation 2/ is redundant so remove it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-8-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Avoid doing a copy of the parameter pageMiquel Raynal1-15/+15
There is no need for copying the parameter page, playing with pointers does the trick. There is not functional change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-7-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Define the number of parameter pagesMiquel Raynal1-5/+11
Use a macro to define the number of parameter page instead of hardcoding it everywhere. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-6-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Use intermediate variables to improve readabilityMiquel Raynal1-4/+5
Before reworking a little bit the ONFI detection code, let's clean the coding style of the if statements to improve readability. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-5-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Fix redundancy detection checkMiquel Raynal1-1/+1
During ONFI detection, the CRC derived from the parameter page and the CRC supposed to be at the end of the parameter page are compared. If they do not match, the second then the third copies of the page are tried. The current implementation compares the newly derived CRC with the CRC contained in the first page only. So if this particular CRC area has been corrupted, then the detection will fail for a wrong reason. Fix this issue by checking the derived CRC against the right one. Fixes: 39138c1f4a31 ("mtd: rawnand: use bit-wise majority to recover the ONFI param page") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-4-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: timings: Fix default tR_max and tCCS_min timingsMiquel Raynal1-3/+2
tR and tCCS are currently wrongly expressed in femtoseconds, while we expect these values to be expressed in picoseconds. Set right hardcoded values. Fixes: 6a943386ee36 mtd: rawnand: add default values for dynamic timings Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-3-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: timings: Add mode information to the timings structureMiquel Raynal1-0/+6
Convert the timings union into a structure containing the mode and the actual values. The values are still a union in prevision of the addition of the NVDDR modes. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200428094302.14624-2-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Rename the ->correct() functionMiquel Raynal1-10/+9
There is no correction involved at this point, it is just a matter of reading registers and checking whether bitflips have occurred or not. Rename the function to clarify it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-7-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Rename a function to clarifyMiquel Raynal1-3/+3
Cosmetic change to clarify the purpose of the function. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-6-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Fix probe error pathMiquel Raynal1-9/+14
Ensure all chips are deregistered and cleaned in case of error during the probe. Fixes: 02f26ecf8c77 ("mtd: nand: add reworked Marvell NAND controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-5-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Use nand_cleanup() when the device is not yet registeredMiquel Raynal1-1/+1
Do not call nand_release() while the MTD device has not been registered, use nand_cleanup() instead. Fixes: 02f26ecf8c77 ("mtd: nand: add reworked Marvell NAND controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-4-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Use devm_platform_ioremap_res()Miquel Raynal1-3/+1
Switch from the old platform_get_resource()/devm_ioremap_resource() couple to the newer devm_platform_ioremap_resource() helper. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-3-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: marvell: Fix the condition on a return codeMiquel Raynal1-1/+1
In a previous fix, I changed the condition on which the timeout of an IRQ is reached from: if (!ret) into: if (ret && !pending) While having a non-zero return code is usual in the Linux kernel, here ret comes from a wait_for_completion_timeout() which returns 0 when the waiting period is too long. Hence, the revised condition should be: if (!ret && !pending) The faulty patch did not produce any error because of the !pending condition so this change is finally purely cosmetic and does not change the actual driver behavior. Fixes: cafb56dd741e ("mtd: rawnand: marvell: prevent timeouts on a loaded machine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200424164501.26719-2-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Give more information about the ECC weaknessMiquel Raynal1-2/+4
When the ECC strength is too weak compared to the NAND chip requirements, display the values so that it is clear for people how much they are far from the requirements (and might get in troubles in the future). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200421163906.7515-1-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: au1550nd: Patch the read/write buf helper prototypesBoris Brezillon1-13/+17
To match the types passed by au1550nd_exec_instr() function. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200419193037.1544035-5-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: au1550nd: Get rid of the legacy interface implementationBoris Brezillon1-264/+0
Now that exec_op() is implemented we can get rid of all other hooks. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200419193037.1544035-4-boris.brezillon@collabora.com
2020-05-10mtd: rawnand: au1550nd: Implement exec_op()Boris Brezillon1-0/+110
So we can later get rid of the legacy interface implementation. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200419193037.1544035-3-boris.brezillon@collabora.com
2020-05-10mtd: rawnand: au1550nd: Stop using IO_ADDR_{R, W} in au_{read, write}_buf[16]()Boris Brezillon1-4/+13
We are about to re-use those for the exec_op() implementation which will not rely on au1550_hwcontrol(). Let's patch those helpers to simply use the iomem address stored in the context. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200419193037.1544035-2-boris.brezillon@collabora.com
2020-05-10mtd: rawnand: denali: add more delays before latching incoming dataMasahiro Yamada1-11/+34
The Denali IP have several registers to specify how many clock cycles should be waited between falling/rising signals. You can improve the NAND access performance by programming these registers with optimized values. Because struct nand_sdr_timings represents the device requirement in pico seconds, denali_setup_data_interface() computes the register values by dividing the device timings with the clock period. Marek Vasut reported this driver in the latest kernel does not work on his SOCFPGA board. (The on-board NAND chip is mode 5) The suspicious parameter is acc_clks, so this commit relaxes it. The Denali NAND Flash Memory Controller User's Guide describes this register as follows: acc_clks signifies the number of bus interface clk_x clock cycles, controller should wait from read enable going low to sending out a strobe of clk_x for capturing of incoming data. Currently, acc_clks is calculated only based on tREA, the delay on the chip side. This does not include additional delays that come from the data path on the PCB and in the SoC, load capacity of the pins, etc. This relatively becomes a big factor on faster timing modes like mode 5. Before supporting the ->setup_data_interface() hook (e.g. Linux 4.12), the Denali driver hacks acc_clks in a couple of ways [1] [2] to support the timing mode 5. We would not go back to the hard-coded acc_clks, but we need to include this factor into the delay somehow. Let's say the amount of the additional delay is 10000 pico sec. In the new calculation, acc_clks is determined by timings->tREA_max + data_setup_on_host. Also, prolong the RE# low period to make sure the data hold is met. Finally, re-center the data latch timing for extra safety. [1] https://github.com/torvalds/linux/blob/v4.12/drivers/mtd/nand/denali.c#L276 [2] https://github.com/torvalds/linux/blob/v4.12/drivers/mtd/nand/denali.c#L282 Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200317071821.9916-1-yamada.masahiro@socionext.com
2020-05-10mtd: rawnand: Take check_only into accountBoris Brezillon11-10/+33
->exec_op() is passed a check_only argument that encodes when the controller should just check whether the operation is supported or not without executing it. Some controllers simply ignore this arguments, others don't but keep modifying some of the registers before returning. Let's fix all those drivers. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200418194217.1016060-1-boris.brezillon@collabora.com
2020-05-10mtd: rawnand: brcmnand: Remove unused including <linux/version.h>YueHaibing1-1/+0
Remove including <linux/version.h> that don't need it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200417101129.35556-1-yuehaibing@huawei.com
2020-05-10mtd: rawnand: cadence: Make cadence_nand_attach_chip staticYueHaibing1-1/+1
Fix sparse warning: drivers/mtd/nand/raw/cadence-nand-controller.c:2595:5: warning: symbol 'cadence_nand_attach_chip' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200410115228.30440-1-yuehaibing@huawei.com
2020-05-10mtd: rawnand: ingenic: Make qi_lb60_ooblayout_ops staticYueHaibing1-1/+1
Fix sparse warning: drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:105:32: warning: symbol 'qi_lb60_ooblayout_ops' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200410115121.11852-1-yuehaibing@huawei.com
2020-05-10mtd: rawnand: fsmc: Change to non-atomic bit operationsFenghua Yu1-3/+4
No need to use expensive atomic change_bit() on dat[] and err_idx[]: 1. fsmc_bch8_correct_data() is called while mutex chip->lock is held 2. err_idx[] is a local variable. To avoid big endian concern due to type cast to unsigned long, directly change the bit in the specified byte instead of using non-atomic __change_bit(). Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1576886755-9788-1-git-send-email-fenghua.yu@intel.com
2020-05-10bdi: remove the name field in struct backing_dev_infoChristoph Hellwig1-1/+0
The name is only printed for a not registered bdi in writeback. Use the device name there as is more useful anyway for the unlike case that the warning triggers. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Jan Kara <jack@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-05-10bdi: simplify bdi_allocChristoph Hellwig1-1/+1
Merge the _node vs normal version and drop the superflous gfp_t argument. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Jan Kara <jack@suse.cz> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-04-30mtd: cfi_cmdset_0001: Support the absence of protection registersJean-Philippe Brucker1-5/+8
The flash controller implemented by the Arm Base platform behaves like the Intel StrataFlash J3 device, but omits several features. In particular it doesn't implement a protection register, so "Number of Protection register fields" in the Primary Vendor-Specific Extended Query, is 0. The Intel StrataFlash J3 datasheet only lists 1 as a valid value for NumProtectionFields. It describes the field as: "Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection bytes are available" While a value of 0 may arguably not be architecturally valid, the driver's current behavior is certainly wrong: if NumProtectionFields is 0, read_pri_intelext() adds a negative value to the unsigned extra_size, and ends up in an infinite loop. Fix it by ignoring a NumProtectionFields of 0. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-29mtd: spi-nor: Fix description of the sr_ready() return valueTudor Ambarus1-4/+4
The functions return 1 if ready, 0 if not ready, -errno on errors. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-29mtd: spi-nor: Uniformize the return value in spi_nor_*_ready()Tudor Ambarus1-1/+1
spi_nor_ready() returns 1 if ready, 0 if not ready and -errno on errors. Do the same in all the spi_nor_*_ready() children. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-29mtd: spi-nor: micron-st: Enable locking for n25q00Jungseung Lee1-0/+2
n25q00 uses the 4 bit Block Protection scheme and supports Top/Bottom protection via the BP and TB bits of the Status Register. Enable locking for n25q00. Tested with cirrus controller. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: macronix: Add support for mx25u51245gMason Yang1-0/+3
mx25u51245g is a mass production for new design and replace mx66u51235f(phase out). Validated by read, erase, read back, write and read back on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host (driver/spi/spi-mxic.c). Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: macronix: Add support for mx25l51245gMason Yang1-0/+3
mx25l51245g is a mass production for new design and replace mx66l51235l(phase out). Validated by read, erase, read back, write and read back on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host (driver/spi/spi-mxic.c). Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 16:46:29 +0300