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2020-05-30mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev DPratyush Yadav2-3/+9
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to reflect that. The check for rev A or later compared the BFPT header length with the maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so was the BFPT length for both rev A and B, this check worked fine. But now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT parsing for rev A or B, since their length is 16. So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the next two versions. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-30mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widthsPratyush Yadav1-0/+1
JESD216D.01 says that when the address width can be 3 or 4, it defaults to 3 and enters 4-byte mode when given the appropriate command. So, when we see a configurable width, default to 3 and let flash that default to 4 change it in a post-bfpt fixup. This fixes SMPT parsing for flashes with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: Add support for Cypress cy15x104qSascha Hauer1-0/+2
The Cypress cy15b104q and cy15v104q are 4Mbit serial SPI F-RAM devices. Add support for them to the spi-nor driver. The actual Device ID of this chip is 7f 7f 7f 7f 7f 7f c2 2c 04. That is six times the continuation code 7f followed by c2 for Ramtron. Unfortunately the chip sends the Device ID in reversed order, so the continuation code is not at the beginning, but instead at the end. Even more unfortunate is that when reading further the chip sends more 7f codes which means we are not even able to count the continuation codes. We can only hope that this reversed Device ID will never match any other devices ID. Collisions are improbable as of now, the solution from above is good enough. In case of future collisions one can introduce an INFO9 macro, with the downsize that struct flash_info would grow and we have lots of flashes. A more elegant solution would be to introduce dedicated flash ID tables for each bank in JESP106BA. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [tudor.ambarus@microchip.com: amend commit description with possible future solutions in case collisions occur.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: Fix SPI NOR acronymTudor Ambarus6-9/+9
The correct terminology is serial NOR flash or SPI NOR. s/SPI-NOR/SPI NOR and s/spi-nor/SPI NOR across the subsystem. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2020-05-28mtd: spi-nor: spansion: Differentiate between s25fl256s and s25fs256sTudor Ambarus1-6/+12
s25fs256s was identified as s25fl256s. Differentiate between them by the Family ID using the INFO6 macro. Fixes: b199489d37b2 ("mtd: spi-nor: add the framework for SPI NOR") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
2020-05-28mtd: spi-nor: Add support for s25fs128s1Yicong Yang1-0/+3
Add support for Cypress s25fs128s1 flash. Previously the flash is decoded as s25fl129p1 by mistake. Add it in the flash info list to correctly decode. The flash also needs a fixup for s25fs-s family. Further capability of the flash will be parsed from bfpt. The flash has been tested under SPI/DUAL/QUAD mode on hisi-sfc-v3xx controller, all the write/read/erase works well. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: spansion: fix writes on S25FS512SSergei Shtylyov1-2/+23
Spansion S25FS-S family has an issue in the Basic Flash Parameter Table (BFPT): Dword-11 bits 7:4 specify a page size of 512 bytes. Actually this is configurable in the vendor unique register (CR3V) and even the factory default setting is to "wrap at 256 bytes", so blindly relying on BFPT breaks the page writes on these chips. Add the post-BFPT fixup which restores the default page size of 256 bytes -- to properly read CR3V this early is quite intrusive and should better be done as a new feature; Alexander Sverdlin had the patch doing that: https://patchwork.ozlabs.org/project/linux-mtd/patch/20200227123657.26030-1-alexander.sverdlin@nokia.com/ Fixes: dfd2b74530e ("mtd: spi-nor: add Spansion S25FS512S ID") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-26mtd: rawnand: ams-delta: Stop using nand_release()Miquel Raynal1-1/+4
This helper is not very useful and very often people get confused: they use nand_release() instead of nand_cleanup(). Let's stop using nand_release() by calling mtd_device_unregister() and nand_cleanup() directly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200519130035.1883-2-miquel.raynal@bootlin.com
2020-05-26mtd: rawnand: arasan: Support the hardware BCH ECC engineMiquel Raynal2-0/+343
Add support for the hardware ECC BCH engine. Please mind that this engine has an important limitation: BCH implementation does not inform the user when an uncorrectable ECC error occurs. To workaround this, we avoid using the hardware engine in the read path and do the computation with the software BCH implementation, which is faster than mixing hardware (for correction) and software (for verification). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-9-miquel.raynal@bootlin.com
2020-05-24mtd: rawnand: arasan: Add new Arasan NAND controllerMiquel Raynal3-0/+963
Add the Arasan NAND controller driver. This brings only NAND controller support. The ECC engine being a bit subtle, hardware ECC support will be added in a second time. This work is based on contributions from Naga Sureshkumar Relli. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-8-miquel.raynal@bootlin.com
2020-05-24mtd: rawnand: Add nand_extract_bits()Miquel Raynal1-0/+44
There are cases where ECC bytes are not byte-aligned. Indeed, BCH implies using a number of ECC bits, which are not always a multiple of 8. We then need a helper like nand_extract_bits() to extract these syndromes from a buffer. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-5-miquel.raynal@bootlin.com
2020-05-24mtd: rawnand: Ensure the number of bitflips is consistentMiquel Raynal1-5/+5
The main NAND read page function can loop over "page reads" many times in if the reading reports uncorrectable error(s) and if the chip supports the read_retry feature. In this case, the number of bitflips is summarized between attempts. Fix this by re-initializing the entire mtd_ecc_stats object each time we retry. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-4-miquel.raynal@bootlin.com
2020-05-24lib/bch: Allow easy bit swappingMiquel Raynal2-2/+2
It seems that several hardware ECC engine use a swapped representation of bytes compared to software. This might having to do with how the ECC engine is wired to the NAND controller or the order the bits are passed to the hardware BCH logic. This means that when the software BCH engine is working in conjunction with data generated with hardware, sometimes we might need to swap the bits inside bytes, eg: 0x0A = b0000_1010 -> b0101_0000 = 0x50 Make it possible by adding a boolean to the BCH initialization routine. Regarding the implementation itself, this is a rather simple approach that can probably be enhanced in the future by preparing the ->a_{mod,pow}_tab tables with the swapping in mind. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-3-miquel.raynal@bootlin.com
2020-05-24lib/bch: Rework a little bit the exported function namesMiquel Raynal2-10/+10
There are four exported functions, all suffixed by _bch, which is clearly not the norm. Let's rename them by prefixing them with bch_ instead. This is a mechanical change: init_bch -> bch_init free_bch -> bch_free encode_bch -> bch_encode decode_bch -> bch_decode Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-2-miquel.raynal@bootlin.com
2020-05-24mtd: rawnand: micron: Adapt the PAGE READ flow to constraint controllersMiquel Raynal1-9/+52
There are controllers not able to just read data cycles on the bus. There are controllers not able to do a change column. If we want to support both, we need to check which operation is supported first. This is the exact same mechanism that is in use for parameter page reads (ONFI/JEDEC) as the same problem occurs. Speed testing does not show any throughput penalty so we do not optimize more than that. However it is likely that, in the future, a more robust and exhaustive test will run at boot time to avoid re-checking what is supported and what is not at every call. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519130834.2918-1-miquel.raynal@bootlin.com
2020-05-24mtd: rawnand: Remove the cmx270 NAND controller driverBoris Brezillon3-241/+0
The CM-X270 board has been removed, we can remove the custom NAND driver as well. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200518163300.304732-1-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: Fix nand_gpio_waitrdy()Boris Brezillon1-2/+8
Mimic what's done in nand_soft_waitrdy() and add one to the jiffies timeout so we don't end up waiting less than actually required. Reported-by: Tudor Ambarus <tudor.ambarus@microchip.com> Fixes: b0e137ad24b6c ("mtd: rawnand: Provide helper for polling GPIO R/B pin") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200518155237.297549-1-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: davinci: Get rid of the legacy interface implementationBoris Brezillon1-91/+0
Now that exec_op() is implemented we can get rid of the legacy interface implementation. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200513172248.141402-4-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: davinci: Implement exec_op()Boris Brezillon1-1/+101
Implement exec_op() so we can later get rid of the legacy interface implementation. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200513172248.141402-3-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: davinci: Stop using nand_chip.legacy.IO_ADDR_{R, W}Boris Brezillon1-21/+15
We can use info->current_cs directly instead of doing this weird IO_ADDR_{R,W} re-assignment dance. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200513172248.141402-2-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: davinci: Inherit from nand_controllerBoris Brezillon1-1/+4
Let's not rely on the dummy_controller embedded in nand_chip.legacy and explicitly inherit from nand_controller instead. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200513172248.141402-1-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: brcmnand: correctly verify erased pagesÁlvaro Fernández Rojas1-8/+11
The current code checks that the whole OOB area is erased. This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will fail due to the usable OOB bytes not being 0xff. Correct this by only checking that data and ECC bytes aren't 0xff. Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com
2020-05-24mtd: rawnand: brcmnand: improve hamming oob layoutÁlvaro Fernández Rojas1-19/+16
The current code generates 8 oob sections: S1 1-5 ECC 6-8 S2 9-15 S3 16-21 ECC 22-24 S4 25-31 S5 32-37 ECC 38-40 S6 41-47 S7 48-53 ECC 54-56 S8 57-63 Change it by merging continuous sections: S1 1-5 ECC 6-8 S2 9-21 ECC 22-24 S3 25-37 ECC 38-40 S4 41-53 ECC 54-56 S5 57-63 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512075733.745374-3-noltari@gmail.com
2020-05-24mtd: rawnand: brcmnand: fix hamming oob layoutÁlvaro Fernández Rojas1-4/+7
First 2 bytes are used in large-page nand. Fixes: ef5eeea6e911 ("mtd: nand: brcm: switch to mtd_ooblayout_ops") Cc: stable@vger.kernel.org Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200512075733.745374-2-noltari@gmail.com
2020-05-24mtd: rawnand: Propage CS selection to sub operationsBoris Brezillon1-1/+2
Some controller using the instruction parse infrastructure might need to know which CS a specific sub-operation is targeting. Let's propagate this information. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200505101353.1776394-2-boris.brezillon@collabora.com
2020-05-24mtd: rawnand: stm32_fmc2: use FIELD_PREP/FIELD_GET macrosChristophe Kerello1-92/+85
This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1589284068-4079-3-git-send-email-christophe.kerello@st.com
2020-05-24mtd: rawnand: stm32_fmc2: cosmetic change to use nfc instead of fmc2 where ↵Christophe Kerello1-407/+403
relevant This patch renames functions and local variables. This cleanup is done to get all functions starting by stm32_fmc2_nfc in the FMC2 raw NAND driver when all functions will start by stm32_fmc2_ebi in the FMC2 EBI driver. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1589284068-4079-2-git-send-email-christophe.kerello@st.com
2020-05-20Merge tag 'fixes-for-5.7-rc6' of ↵Linus Torvalds3-3/+6
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD fixes from Richard Weinberger: - Fix a PM regression in brcmnand driver - Propagate ECC information correctly on SPI-NAND - Make sure no MTD name is used multiple time in nvmem * tag 'fixes-for-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd:rawnand: brcmnand: Fix PM resume crash mtd: Fix mtd not registered due to nvmem name collision mtd: spinand: Propagate ECC information to the MTD structure
2020-05-20Merge tag 'for-linus-5.7-rc6' of ↵Linus Torvalds1-10/+2
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI and UBIFS fixes from Richard Weinberger: - Correctly set next cursor for detailed_erase_block_info debugfs file - Don't use crypto_shash_descsize() for digest size in UBIFS - Remove broken lazytime support from UBIFS * tag 'for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubi: Fix seq_file usage in detailed_erase_block_info debugfs file ubifs: fix wrong use of crypto_shash_descsize() ubifs: remove broken lazytime support
2020-05-19mtd:rawnand: brcmnand: Fix PM resume crashKamal Dasu1-2/+1
This change fixes crash observed on PM resume. This bug was introduced in the change made for flash-edu support. Fixes: a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2020-05-18mtd: Fix mtd not registered due to nvmem name collisionRicardo Ribalda Delgado1-1/+1
When the nvmem framework is enabled, a nvmem device is created per mtd device/partition. It is not uncommon that a device can have multiple mtd devices with partitions that have the same name. Eg, when there DT overlay is allowed and the same device with mtd is attached twice. Under that circumstances, the mtd fails to register due to a name duplication on the nvmem framework. With this patch we use the mtdX name instead of the partition name, which is unique. [ 8.948991] sysfs: cannot create duplicate filename '/bus/nvmem/devices/Production Data' [ 8.948992] CPU: 7 PID: 246 Comm: systemd-udevd Not tainted 5.5.0-qtec-standard #13 [ 8.948993] Hardware name: AMD Dibbler/Dibbler, BIOS 05.22.04.0019 10/26/2019 [ 8.948994] Call Trace: [ 8.948996] dump_stack+0x50/0x70 [ 8.948998] sysfs_warn_dup.cold+0x17/0x2d [ 8.949000] sysfs_do_create_link_sd.isra.0+0xc2/0xd0 [ 8.949002] bus_add_device+0x74/0x140 [ 8.949004] device_add+0x34b/0x850 [ 8.949006] nvmem_register.part.0+0x1bf/0x640 ... [ 8.948926] mtd mtd8: Failed to register NVMEM device Fixes: c4dfa25ab307 ("mtd: add support for reading MTD devices via the nvmem API") Signed-off-by: Ricardo Ribalda Delgado <ribalda@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2020-05-18mtd: spinand: Propagate ECC information to the MTD structureMiquel Raynal1-0/+4
This is done by default in the raw NAND core (nand_base.c) but was missing in the SPI-NAND core. Without these two lines the ecc_strength and ecc_step_size values are not exported to the user through sysfs. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2020-05-18ubi: Fix seq_file usage in detailed_erase_block_info debugfs fileRichard Weinberger1-10/+2
3bfa7e141b0b ("fs/seq_file.c: seq_read(): add info message about buggy .next functions") showed that we don't use seq_file correctly. So make sure that our ->next function always updates the position. Fixes: 7bccd12d27b7 ("ubi: Add debugfs file for tracking PEB state") Signed-off-by: Richard Weinberger <richard@nod.at>
2020-05-11mtd: rawnand: stm32_fmc2: use FMC2_TIMEOUT_MS for timeoutsChristophe Kerello1-5/+4
This patch removes the constant FMC2_TIMEOUT_US. FMC2_TIMEOUT_MS will be used each time that we need to wait (except when the timeout value is set by the framework). It was seen, during stress tests with the sequencer in an overloaded system, that we could be close to 1 second, even if we never met this value. To be safe, FMC2_TIMEOUT_MS is set to 5 seconds. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1588756279-17289-4-git-send-email-christophe.kerello@st.com
2020-05-11mtd: rawnand: stm32_fmc2: remove useless inline commentsChristophe Kerello1-40/+0
Remove inline comments that are useless since function label are self explanatory. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1588756279-17289-3-git-send-email-christophe.kerello@st.com
2020-05-11mtd: rawnand: stm32_fmc2: manage all errors cases at probe timeChristophe Kerello1-6/+11
This patch defers its probe when the expected reset control is not yet ready. This patch also handles properly all errors cases at probe time. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1588756279-17289-2-git-send-email-christophe.kerello@st.com
2020-05-11mtd: rawnand: diskonchip: Get rid of the legacy interface implementationBoris Brezillon1-292/+0
Now that exec_op() has been implemented we can get rid of the legacy interface implementation. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501143917.1388957-6-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: diskonchip: Implement exec_op()Boris Brezillon1-20/+199
Implement exec_op() so we can later get rid of the legacy implementation. It's worth noting that the new implementation assert/deassert the CE pin on each operation, which might not be necessary. We also dropped the extra reset done at chip selection time on DOC2001plus. If it's needed we really should do something smarter, because having a reset everytime we access the chip is not that great perf-wise. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501143917.1388957-5-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: diskonchip: Inherit from nand_controllerBoris Brezillon1-0/+3
Stop relying on the dummy controller object embedded in nand_chip.legacy and explicitly inherit from nand_controller. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501143917.1388957-4-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: diskonchip: Get rid of doc2000_readbuf_dword()Boris Brezillon1-21/+9
The logic can easily be merged in doc2000_readbuf(). Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501143917.1388957-3-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: diskonchip: Make sure doc2001plus_readbuf() works for single ↵Boris Brezillon1-3/+6
byte reads Single byte accesses normally go through read_byte() but we are about to use this function in the exec_op() implementation and thus needs to prepare for single byte reads. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200501143917.1388957-2-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: diskonchip: Set the NAND_NO_BBM_QUIRK flagBoris Brezillon1-9/+1
We have a dummy block_bad() implementation returning 0. Let's set the NAND_NO_BBM_QUIRK flag and let the core take care of that. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200511064917.6255-3-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: cafe: Set the NAND_NO_BBM_QUIRK flagBoris Brezillon1-9/+2
We have a dummy block_bad() implementation returning 0. Let's set the NAND_NO_BBM_QUIRK flag and let the core take care of that. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200511064917.6255-2-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: Add a NAND_NO_BBM_QUIRK flagBoris Brezillon1-0/+3
Some controllers with embedded ECC engines override the BBM marker with data or ECC bytes, thus making bad block detection through bad block marker impossible. Let's flag those chips so the core knows it shouldn't check the BBM and consider all blocks good. This should allow us to get rid of two implementers of the legacy.block_bad() hook. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200511064917.6255-1-boris.brezillon@collabora.com
2020-05-11mtd: rawnand: micron: Allow controllers to overload raw accessorsMiquel Raynal1-2/+4
Some controller drivers do not support executing regular nand_read/write_page_raw() helpers. For that, we created nand_monolithic_read/write_page_raw() alternatives. Let's now allow the driver to overload the ECC ->read/write_page_raw() hooks when these hooks are supported. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-14-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Allow controllers to overload soft ECC hooksMiquel Raynal1-4/+8
Some controller drivers do not support executing regular nand_read/write_page_raw() helpers. For that, we created nand_monolithic_read/write_page_raw() alternatives. Let's now allow the driver to overload the ECC ->read/write_page_raw() hooks. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-13-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Expose monolithic read/write_page_raw() helpersMiquel Raynal1-0/+77
The current nand_read/write_page_raw() helpers are already widely used but do not fit the purpose of "constrained" controllers which cannot, for instance, separate command/address cycles with data cycles. Workaround this issue by proposing alternative helpers that can be used by these controller drivers instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-12-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: jedec: Adapt the parameter page read to constraint controllersMiquel Raynal1-6/+13
We already know that there are controllers not able to read the three copies of the parameter page in one go. The workaround was to first request the controller to assert command and address cycles on the NAND bus to trigger a parameter page read, and then do a read operation for each page. But there are also controllers which are not able to split the parameter page read between the command/address cycles and the actual data operation. Let's use a regular PARAMETER PAGE READ operation for the first iteration and use eithe a CHANGE READ COLUMN or a simple DATA READ operation for the following copies, depending on what the controller supports. The default for non-exec-op compliant drivers remains unchanged: use a SIMPLE READ. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-11-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: onfi: Adapt the parameter page read to constraint controllersMiquel Raynal1-7/+14
We already know that there are controllers not able to read the three copies of the parameter page in one go. The workaround was to first request the controller to assert command and address cycles on the NAND bus to trigger a parameter page read, and then do a simple read operation for each page. But there are also controllers which are not able to split the parameter page read between the command/address cycles and the actual data operation. Let's use a regular PARAMETER PAGE READ operation for the first iteration and use either a CHANGE READ COLUMN or a simple DATA READ operation for the following copies, depending on what the controller supports. The default behavior for non-exec-op compliant drivers remains the same: DATA READ. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-10-miquel.raynal@bootlin.com
2020-05-11mtd: rawnand: Give the possibility to verify a read operation is supportedMiquel Raynal7-30/+43
This can be used to discriminate between two path in the parameter page detection: use data_in cycles (like before) if supported, use the CHANGE READ COLUMN command otherwise. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-9-miquel.raynal@bootlin.com
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