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2022-03-14mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizesAmit Kumar Mahapatra1-6/+5
While calculating speed during mtd_speedtest, the time interval (i.e., start - finish) is rounded off to the nearest milliseconds by ignoring the fractional part. This leads to miscalculation of speed. The miscalculation is more visible while running speed test on small partition sizes(i.e., when partition size is equal to eraseblock size or twice the eraseblock size) at higher spi frequencies. For e.g., while calculating eraseblock read speed for a mtd partition with size equal to the eraseblock size(i.e., 64KiB) the eraseblock read time interval comes out to be 966490 nanosecond. This is then converted to millisecond(i.e., 0.966 msec.). The integer part (i.e., 0 msec) of the value is considered and the fractional part (i.e., 0.966) is ignored,for calculating the eraseblock read speed. So the reported eraseblock read speed is 0 KiB/s, which is incorrect. There are two approaches to fix this issue. First approach will be to keep the time interval in millisecond. and round up the integer value, with this approach the 0.966msec time interval in the above example will be rounded up to 1msec and this value is used for calculating the speed. Downside of this approach is that the reported speed is still not accurate. Second approach will be to convert the time interval to microseconds instead of milliseconds, with this approach the 966490 nanosecond time interval in the above example will be converted t0 966.490usec and this value is used for calculating the speed. As compared to the current implementation and the suggested First approach, this approach will report a more accurate speed. Downside of this approach is that, in future if the mtd size is too large then the u64 variable, that holds the number of bytes, might overflow. In this patch we have gone with the second approach as this reports a more accurate speed. With this approach the eraseblock read speed in the above example comes out to be 132505 KiB/s when the spi clock is configured at 150Mhz. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220208103905.13354-1-amit.kumar-mahapatra@xilinx.com
2022-03-14mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_initXin Xiong1-3/+11
The reference counting issue happens in several error handling paths on a refcounted object "nc->dmac". In these paths, the function simply returns the error code, forgetting to balance the reference count of "nc->dmac", increased earlier by dma_request_channel(), which may cause refcount leaks. Fix it by decrementing the refcount of specific object in those error paths. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Co-developed-by: Xiyu Yang <xiyuyang19@fudan.edu.cn> Signed-off-by: Xiyu Yang <xiyuyang19@fudan.edu.cn> Co-developed-by: Xin Tan <tanxin.ctf@gmail.com> Signed-off-by: Xin Tan <tanxin.ctf@gmail.com> Signed-off-by: Xin Xiong <xiongx18@fudan.edu.cn> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220304085330.3610-1-xiongx18@fudan.edu.cn
2022-03-14mtd: rawnand: rockchip: fix platform_get_irq.cocci warningYihao Han1-1/+0
Remove dev_err() messages after platform_get_irq*() failures. platform_get_irq() already prints an error. Generated by: scripts/coccinelle/api/platform_get_irq.cocci Signed-off-by: Yihao Han <hanyihao@vivo.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220303123431.3170-1-hanyihao@vivo.com
2022-03-08mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is setTudor Ambarus1-1/+2
Even if SPI_NOR_NO_ERASE was set, one could still send erase opcodes to the flash. It is not recommended to send unsupported opcodes to flashes. Fix the logic and do not set mtd->_erase when SPI_NOR_NO_ERASE is specified. With this users will not be able to issue erase opcodes to flashes and instead they will recive an -ENOTSUPP error. Fixes: b199489d37b2 ("mtd: spi-nor: add the framework for SPI NOR") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220228163334.277730-1-tudor.ambarus@microchip.com
2022-03-07mtd: rawnand: omap2: Actually prevent invalid configuration and build errorRoger Quadros1-2/+1
The root of the problem is that we are selecting symbols that have dependencies. This can cause random configurations that can fail. The cleanest solution is to avoid using select. This driver uses interfaces from the OMAP_GPMC driver so we have to depend on it instead. Fixes: 4cd335dae3cf ("mtd: rawnand: omap2: Prevent invalid configuration and build error") Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/linux-mtd/20220219193600.24892-1-rogerq@kernel.org
2022-02-28Merge 5.17-rc6 into char-misc-nextGreg Kroah-Hartman8-29/+50
We need the char-misc fixes in here. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-25Merge tag 'char-misc-5.17-rc6' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver fixes from Greg KH: "Here are a few small driver fixes for 5.17-rc6 for reported issues. The majority of these are IIO fixes for small things, and the other two are a mvmem and mtd core conflict fix. All of these have been in linux-next with no reported issues" * tag 'char-misc-5.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: mtd: core: Fix a conflict between MTD and NVMEM on wp-gpios property nvmem: core: Fix a conflict between MTD and NVMEM on wp-gpios property iio: imu: st_lsm6dsx: wait for settling time in st_lsm6dsx_read_oneshot iio: Fix error handling for PM iio: addac: ad74413r: correct comparator gpio getters mask usage iio: addac: ad74413r: use ngpio size when iterating over mask iio: addac: ad74413r: Do not reference negative array offsets iio: adc: men_z188_adc: Fix a resource leak in an error handling path iio: frequency: admv1013: remove the always true condition iio: accel: fxls8962af: add padding to regmap for SPI iio:imu:adis16480: fix buffering for devices with no burst mode iio: adc: ad7124: fix mask used for setting AIN_BUFP & AIN_BUFM bits iio: adc: tsc2046: fix memory corruption by preventing array overflow
2022-02-25mtd: spi-nor: renumber flagsMichael Walle1-14/+14
As we have deleted some flag, lets renumber them so there are no holes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-33-michael@walle.cc
2022-02-25mtd: spi-nor: slightly change code style in spi_nor_sr_ready()Michael Walle1-1/+2
Now that there is almost no special case code left in spi_nor_sr_ready(), the return check looks odd. Move the function call closer to the return code checking. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-32-michael@walle.cc
2022-02-25mtd: spi-nor: spansion: rename vendor specific functions and definesMichael Walle1-7/+7
Drop the generic spi_nor prefix for all the spansion functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-31-michael@walle.cc
2022-02-25mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flagMichael Walle3-27/+34
Now that all functions using that flag are local to the spansion module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-30-michael@walle.cc
2022-02-25mtd: spi-nor: move all spansion specifics into spansion.cMichael Walle2-49/+70
The clear status register flags is only available on spansion flashes. Move all the functions around that into the spanion module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-29-michael@walle.cc
2022-02-25mtd: spi-nor: spansion: slightly rework control flow in late_init()Michael Walle1-7/+6
Don't return early when the flash is smaller than or equal to 16MiB. We need to be able to register hooks for all sizes of flashes. This also has the benefit that it increases the readability of the code because the action, i.e. registering the fixups, is connected to the condition, i.e. flashes larger than 16MiB. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-28-michael@walle.cc
2022-02-25mtd: spi-nor: micron-st: rename vendor specific functions and definesMichael Walle1-9/+9
Drop the generic spi_nor prefix for all the micron-st functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-27-michael@walle.cc
2022-02-25mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flagMichael Walle3-39/+60
Now that all functions using that flag are local to the micron module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-26-michael@walle.cc
2022-02-25mtd: spi-nor: move all micron-st specifics into micron-st.cMichael Walle2-122/+135
The flag status register is only available on micron flashes. Move all the functions around that into the micron module. This is almost a mechanical move except for the spi_nor_fsr_ready() which now also checks the normal status register. Previously, this was done in spi_nor_ready(). Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-25-michael@walle.cc
2022-02-25mtd: spi-nor: xilinx: correct the debug messageMichael Walle1-1/+1
XRDSR is a combination of xilinx and the RDSR opcode, but the register is just the status register. Correct the debug message. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-24-michael@walle.cc
2022-02-25mtd: spi-nor: xilinx: rename vendor specific functions and definesMichael Walle1-15/+15
Drop the generic spi_nor prefix for all the xilinx functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-23-michael@walle.cc
2022-02-25mtd: spi-nor: move all xilinx specifics into xilinx.cMichael Walle3-81/+74
Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
2022-02-25mtd: spi-nor: guard _page_size parameter in S3AN_INFO()Michael Walle1-2/+2
The _page_size marco parameter was missing parentheses around it. Add them. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-21-michael@walle.cc
2022-02-25mtd: spi-nor: export more functions to be used in vendor modulesMichael Walle2-5/+11
We will move vendor specific code into the vendor modules and thus we will have to export these functions so they can be called. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-20-michael@walle.cc
2022-02-25mtd: spi-nor: allow a flash to define its own ready() functionMichael Walle2-0/+8
Xilinx and Micron flashes have their own implementation of the spi_nor_ready() function. At the moment, the core will figure out which one to call according to some flags. Lay the foundation to make it possible that a flash can register its own ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-19-michael@walle.cc
2022-02-25mtd: spi-nor: slightly refactor the spi_nor_setup()Michael Walle2-9/+9
Instead of always using a function pointer (and initializing it to our default), just call the default function if the flash didn't set its own one. That will make the call flow easier to follow. Also mark the parameter as optional now. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-18-michael@walle.cc
2022-02-25mtd: spi-nor: xmc: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-17-michael@walle.cc
2022-02-25mtd: spi-nor: xilinx: unify function namesMichael Walle1-9/+9
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-16-michael@walle.cc
2022-02-25mtd: spi-nor: winbond: unify function namesMichael Walle1-14/+15
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-15-michael@walle.cc
2022-02-25mtd: spi-nor: sst: unify function namesMichael Walle1-22/+22
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-14-michael@walle.cc
2022-02-25mtd: spi-nor: spansion: unify function namesMichael Walle1-17/+17
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-13-michael@walle.cc
2022-02-25mtd: spi-nor: micron-st: unify function namesMichael Walle1-17/+17
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-12-michael@walle.cc
2022-02-25mtd: spi-nor: macronix: unify function namesMichael Walle1-7/+7
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-11-michael@walle.cc
2022-02-25mtd: spi-nor: issi: unify function namesMichael Walle1-5/+5
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-10-michael@walle.cc
2022-02-25mtd: spi-nor: intel: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-9-michael@walle.cc
2022-02-25mtd: spi-nor: gigadevice: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-8-michael@walle.cc
2022-02-25mtd: spi-nor: fujitsu: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-7-michael@walle.cc
2022-02-25mtd: spi-nor: everspin: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-6-michael@walle.cc
2022-02-25mtd: spi-nor: esmt: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-5-michael@walle.cc
2022-02-25mtd: spi-nor: eon: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-4-michael@walle.cc
2022-02-25mtd: spi-nor: catalyst: unify function namesMichael Walle1-3/+3
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-3-michael@walle.cc
2022-02-25mtd: spi-nor: atmel: unify function namesMichael Walle1-39/+42
To avoid name clashes unify all the function and static object names and use one of the following prefixes which should be sufficiently unique: - <vendor>_nor_ - <flash_family>_nor_ - <flash_part>_ There are no functional changes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-2-michael@walle.cc
2022-02-21mtd: core: Drop duplicate NULL checks around nvmem_unregister()Andy Shevchenko1-9/+4
Since nvmem_unregister() checks for NULL, no need to repeat in the caller. Drop duplicate NULL checks. Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20220220151527.17216-13-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-21mtd: core: Fix a conflict between MTD and NVMEM on wp-gpios propertyChristophe Kerello1-0/+2
Wp-gpios property can be used on NVMEM nodes and the same property can be also used on MTD NAND nodes. In case of the wp-gpios property is defined at NAND level node, the GPIO management is done at NAND driver level. Write protect is disabled when the driver is probed or resumed and is enabled when the driver is released or suspended. When no partitions are defined in the NAND DT node, then the NAND DT node will be passed to NVMEM framework. If wp-gpios property is defined in this node, the GPIO resource is taken twice and the NAND controller driver fails to probe. A new Boolean flag named ignore_wp has been added in nvmem_config. In case ignore_wp is set, it means that the GPIO is handled by the provider. Lets set this flag in MTD layer to avoid the conflict on wp_gpios property. Fixes: 2a127da461a9 ("nvmem: add support for the write-protect pin") Cc: stable@vger.kernel.org Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20220220151432.16605-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-02-18mtd: rawnand: stm32_fmc2: Add NAND Write Protect supportChristophe Kerello1-1/+39
This patch adds the support of the WP# signal. WP will be disabled in probe/resume callbacks and will be enabled in remove/suspend callbacks. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220217144755.270679-3-christophe.kerello@foss.st.com
2022-02-18mtd: rawnand: pl353: Set the nand chip node as the flash nodeAmit Kumar Mahapatra1-1/+1
In devicetree the flash information is embedded within nand chip node, so during nand chip initialization the nand chip node should be passed to nand_set_flash_node() api, instead of nand controller node. Fixes: 08d8c62164a3 ("mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller") Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220209053427.27676-1-amit.kumar-mahapatra@xilinx.com
2022-02-18mtd: parsers: trx: allow to use on MediaTek MIPS SoCsINAGAKI Hiroshi1-1/+1
Buffalo sells some router devices which have trx-formatted firmware, based on MediaTek MIPS SoCs. To use parser_trx on those devices, add "RALINK" to dependency and allow to compile for MediaTek MIPS SoCs. examples: - WCR-1166DS (MT7628) - WSR-1166DHP (MT7621) - WSR-2533DHP (MT7621) Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220213064045.1781-1-musashino.open@gmail.com
2022-02-18mtd: spear_smi: use GFP_KERNELJulia Lawall1-1/+1
Platform_driver probe functions aren't called with locks held and thus don't need GFP_ATOMIC. Use GFP_KERNEL instead. Problem found with Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220210204223.104181-8-Julia.Lawall@inria.fr
2022-02-18Merge tag 'mtd/spi-mem-ecc-for-5.18' into mtd/nextMiquel Raynal7-14/+1054
Topic branch bringing-in changes related to the support of ECC engines that can be used by SPI controllers to manage SPI NANDs as well as possibly by parallel NAND controllers. In particular, it brings support for Macronix ECC engine that can be used with Macronix SPI controller. The changes touch the NAND core, the NAND ECC core, the spi-mem layer, a SPI controller driver and add a new NAND ECC driver, as well as a number of binding updates. Binding changes: * Vendor prefixes: Clarify Macronix prefix * SPI NAND: Convert spi-nand description file to yaml * Raw NAND chip: Create a NAND chip description * Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description * Describe Macronix NAND ECC engine * Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory NAND core changes: * ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: * Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode SPI-NAND core changes: * Delay a little bit the dirmap creation * Create direct mapping descriptors for ECC operations SPI-NAND driver changes: * macronix: Use random program load SPI changes: * Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations * spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure
2022-02-15mtd: spi-nor / spi / MFD: Convert intel-spi to SPI MEMMark Brown6-1181/+0
Merge series from Mika Westerberg <mika.westerberg@linux.intel.com>: Based on discussion on the patch I sent some time ago here: http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html it turns out that the preferred way to deal with the SPI flash controller drivers is through SPI MEM which is part of Linux SPI subsystem. This series does that for the intel-spi driver. This also renames the driver to follow the convention used in the SPI subsystem. The first patch improves the write protection handling to be slightly more safer. The following two patches do the conversion itself. Note the Intel SPI flash controller only allows commands such as read, write and so on and it internally uses whatever addressing etc. it figured from the SFDP on the flash device. base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07
2022-02-14mtd: spi-nor: intel-spi: Convert to SPI MEMMika Westerberg6-1187/+0
The preferred way to implement SPI-NOR controller drivers is through SPI subsubsystem utilizing the SPI MEM core functions. This converts the Intel SPI flash controller driver over the SPI MEM by moving the driver from SPI-NOR subsystem to SPI subsystem and in one go make it use the SPI MEM functions. The driver name will be changed from intel-spi to spi-intel to match the convention used in the SPI subsystem. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220209122706.42439-3-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-14mtd: spi-nor: intel-spi: Disable write protection only if askedMika Westerberg2-32/+38
Currently the driver tries to disable the BIOS write protection automatically even if this is not what the user wants. For this reason modify the driver so that by default it does not touch the write protection. Only if specifically asked by the user (setting writeable=1 command line parameter) the driver tries to disable the BIOS write protection. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220209122706.42439-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-10mtd: spinand: Create direct mapping descriptors for ECC operationsMiquel Raynal1-2/+33
In order for pipelined ECC engines to be able to enable/disable the ECC engine only when needed and avoid races when future parallel-operations will be supported, we need to provide the information about the use of the ECC engine in the direct mapping hooks. As direct mapping configurations are meant to be static, it is best to create two new mappings: one for regular 'raw' accesses and one for accesses involving correction. It is up to the driver to use or not the new ECC enable boolean contained in the spi-mem operation. As dirmaps are not free (they consume a few pages of MMIO address space) and because these extra entries are only meant to be used by pipelined engines, let's limit their use to this specific type of engine and save a bit of memory with all the other setups. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com
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