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path: root/drivers/mtd/spi-nor
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2019-11-01mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()Tudor Ambarus1-53/+64
Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Don't overwrite errno from Reg OpsTudor Ambarus1-7/+6
Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop explicit cast to int to already int valueTudor Ambarus1-9/+6
ret is already of type int. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Stop compare with negative in Reg Ops methodsTudor Ambarus1-10/+13
spi_mem_exec_op() nor->controller_ops->write_reg() nor->controller_ops->read_reg() spi_nor_wait_till_ready() Return 0 on success, -errno otherwise. Stop compare with negative and compare with zero in all the register operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Group all Reg Ops to avoid forward declarationsTudor Ambarus1-213/+213
Group all register methods up in the file, to avoid forward declarations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop duplicated new lineTudor Ambarus1-1/+0
Two new lines, one after another, drop one. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methodsTudor Ambarus1-54/+56
All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definitionTudor Ambarus1-8/+7
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', to comply with the SPI NOR int (*read_reg)() method. The 'const' qualifier has no meaning for parameters passed by value, drop it. Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, drop it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'Tudor Ambarus7-96/+136
Move all SPI NOR controller driver specific ops in a dedicated structure. 'struct spi_nor' becomes lighter. Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'. Rename wite/read_buf to buf, the name of the functions are suggestive enough. Constify buf in int (*write_reg). Comply with these changes in the SPI NOR controller drivers. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignmentTudor Ambarus1-1/+0
The pointer to 'struct spi_nor' is kzalloc'ed above in the code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: add support for en25qh16DENG Qingfang1-0/+2
Tested on HiWiFi C526A Datasheet is available at: http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdf Signed-off-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flashJethro Beekman2-0/+16
Now that SPI flash controllers without a software sequencer are supported, it's trivial to add support for CNL and its PCI ID. Values from https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf Signed-off-by: Jethro Beekman <jethro@fortanix.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-23mtd: spi-nor: intel-spi: support chips without software sequencerJethro Beekman1-7/+16
Some flash controllers don't have a software sequencer. Avoid configuring the register addresses for it, and double check everywhere that its not accidentally trying to be used. Every use of `sregs` is now guarded by a check of `sregs` or `swseq_reg`. The check might be done in the calling function. Signed-off-by: Jethro Beekman <jethro@fortanix.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-04mtd: spi-nor: Fix direction of the write_sr() transferTudor Ambarus1-1/+1
write_sr() sends data to the SPI memory, fix the direction. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Reported-by: John Garry <john.garry@huawei.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: John Garry <john.garry@huawei.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-08-30mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"Ashish Kumar1-1/+4
n25q512a was rebranded to mt25qu512a after its spin off from STM. mt25qu512a is different only in terms of operating frequency, the JEDEC id is the same as in n25q512a. Dual reads are supported (0x3b, 0x3c), set the SPI_NOR_DUAL_READ flag. 4-byte opcodes are supported, set the SPI_NOR_4B_OPCODES flag. Tested Single I/O and QUAD I/O mode on LS1046FRWY. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: rename entry to "mt25qu512a (n25q512a)", reword commit message, order entry by size, drop comment as it looked redundant] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-30mtd: spi-nor: Add support for mt35xu02gAshish Kumar1-0/+3
mt35xu02g is an Octal flash supporting Single and OCTAL I/O. Tested on LS1028ARDB. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: reword commit message] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-29mtd: spi-nor: remove superfluous pass of nor->info->sector_sizeTudor Ambarus1-2/+3
We already pass a pointer to nor, we can obtain the sector_size by dereferencing it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-29mtd: spi-nor: enable the debugfs for the partname and partidZhuohao Lee1-0/+12
This patch adds spi_nor_debugfs_init() for the debugfs initialization. With this patch, we can read the partname and partid through the debugfs. The output of new debugfs nodes on my device are: cat /sys/kernel/debug/mtd/mtd0/partid spi-nor:ef6017 cat /sys/kernel/debug/mtd/mtd0/partname w25q64dw Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-28mtd: spi-nor: hisi-sfc: Add of_node_put() before breakNishka Dasgupta1-0/+1
Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a break from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the break. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-28mtd: spi-nor: aspeed-smc: Add of_node_put()Nishka Dasgupta1-1/+3
Each iteration of for_each_available_child_of_node puts the previous node, but in the case of a break from the middle of the loop, there is no put, thus causing a memory leak. Upon termination of the loop (whether by break or a natural exit), either ret will have a non-zero value or child will be NULL. Hence add an of_node_put() that will execute only when ret has a non-zero value, as calling of_node_put() on a possible NULL value does not cause any further issues. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-28mtd: spi-nor: Introduce spi_nor_get_flash_info()Tudor Ambarus1-32/+44
Dedicate a function for getting the pointer to the flash_info const struct. Trim a bit the spi_nor_scan() huge function. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Introduce spi_nor_set_addr_width()Tudor Ambarus1-20/+30
Parsing of flash parameters were interleaved with setting of the nor addr width. Dedicate a function for setting nor addr width. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Bring flash params init togetherTudor Ambarus1-18/+11
Bring all flash parameters default initialization in spi_nor_legacy_params_init(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add the SPI_NOR_XSR_RDY flagBoris Brezillon1-1/+9
S3AN flashes use a specific opcode to read the status register. We currently use the SPI_S3AN flag to decide whether this specific SR read opcode should be used, but SPI_S3AN is about to disappear, so let's add a new flag. Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and vice versa. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add s3an_post_sfdp_fixups()Tudor Ambarus1-7/+11
s3an_nor_scan() was overriding the opcode selection done in spi_nor_default_setup(). Set nor->setup() method in order to avoid the unnecessary call to spi_nor_default_setup(). Now that the call to spi_nor_default_setup() is skipped, set mtd.erasesize to nor->info->sector_size, as it was when spi_nor_select_erase() was called. No dummy byte is required for the S3AN's Random Read command (0x03), so no need to set nor->read_dummy. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add a ->setup() methodTudor Ambarus1-211/+221
nor->params.setup() configures the SPI NOR memory. Useful for SPI NOR flashes that have peculiarities to the SPI NOR standard, e.g. different opcodes, specific address calculation, page size, etc. Right now the only user will be the S3AN chips, but other manufacturers can implement it if needed. Move spi_nor_setup() related code in order to avoid a forward declaration to spi_nor_default_setup(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add a ->convert_addr() methodBoris Brezillon1-10/+14
In order to separate manufacturer quirks from the core we need to get rid of all the manufacturer specific flags, like the SNOR_F_S3AN_ADDR_DEFAULT one. This can easily be replaced by a ->convert_addr() hook, which when implemented will provide the core with an easy way to convert an absolute address into something the flash understands. Right now the only user are the S3AN chips, but other manufacturers can implement it if needed. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add spansion_post_sfdp_fixups()Boris Brezillon1-14/+23
Add a spansion_post_sfdp_fixups() function to fix the erase opcode, erase sector size and set the SNOR_F_4B_OPCODES flag. This way, all spansion related quirks are placed in the spansion_post_sfdp_fixups() function. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add post_sfdp() hook to tweak flash configBoris Brezillon1-1/+32
SFDP tables are sometimes wrong and we need a way to override the config chosen by the SFDP parsing logic without discarding all of it. Add a new hook called after the SFDP parsing has taken place to deal with such problems. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Rework the SPI NOR lock/unlock logicBoris Brezillon1-13/+37
Add the SNOR_F_HAS_LOCK flag and set it when SPI_NOR_HAS_LOCK is set in the flash_info entry or when it's a Micron or ST flash. Move the locking hooks in a separate struct so that we have just one field to update when we change the locking implementation. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use ->default_init() hook, introduce spi_nor_late_init_params(), set ops in nor->params] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Create a ->set_4byte() methodBoris Brezillon1-37/+39
The procedure used to enable 4 byte addressing mode depends on the NOR device, so let's provide a hook so that manufacturer specific handling can be implemented in a sane way. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use nor->params.set_4byte() instead of nor->set_4byte()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Split spi_nor_init_params()Tudor Ambarus1-20/+63
Add functions to delimit what the chunks of code do: static void spi_nor_init_params() { spi_nor_info_init_params() spi_nor_manufacturer_init_params() spi_nor_sfdp_init_params() } Add descriptions to all methods. spi_nor_init_params() becomes of type void, as all its children return void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Move manufacturer quad_enable() in ->default_init()Tudor Ambarus1-19/+29
The goal is to move the quad_enable manufacturer specific init in the nor->manufacturer->fixups->default_init() The legacy quad_enable() implementation is spansion_quad_enable(), select this method by default. Set specific manufacturer fixups->default_init() hooks to overwrite the default quad_enable() implementation when needed. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add a default_init() fixup hook for gd25q256Boris Brezillon1-12/+16
gd25q256 needs to tweak the ->quad_enable() implementation and the ->default_init() fixup hook is the perfect place to do that. This way, if we ever need to tweak more things for this flash, we won't have to add new fields in flash_info. We can get rid of the flash_info->quad_enable field as gd25q256 was the only user. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> [tudor.ambarus@microchip.com: use ->default_init() hook instead of ->post_sfdp()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Add default_init() hook to tweak flash parametersTudor Ambarus1-0/+17
As of now, the flash parameters initialization logic is as following: a/ default flash parameters init in spi_nor_init_params() b/ manufacturer specific flash parameters updates, split across entire spi-nor core code c/ flash parameters updates based on SFDP tables d/ post BFPT flash parameter updates In the quest of removing the manufacturer specific code from the spi-nor core, we want to impose a timeline/priority on how the flash parameters are updated. The following sequence of calls is pursued: 1/ spi-nor core parameters init based on 'flash_info' struct: spi_nor_info_init_params() which can be overwritten by: 2/ MFR-based manufacturer flash parameters init: nor->manufacturer->fixups->default_init() which can be overwritten by: 3/ specific flash_info tweeks done when decisions can not be done just on MFR: nor->info->fixups->default_init() which can be overwritten by: 4/ SFDP tables flash parameters init - SFDP knows better: spi_nor_sfdp_init_params() which can be overwritten by: 5/ post SFDP tables flash parameters updates - in case manufacturers get the serial flash tables wrong or incomplete. nor->info->fixups->post_sfdp() The later can be extended to nor->manufacturer->fixups->post_sfdp() if needed. This patch opens doors for steps 2/ and 3/. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Move erase_map to 'struct spi_nor_flash_parameter'Tudor Ambarus1-19/+21
All flash parameters and settings should reside inside 'struct spi_nor_flash_parameter'. Move the SMPT parsed erase map from 'struct spi_nor' to 'struct spi_nor_flash_parameter'. Please note that there is a roll-back mechanism for the flash parameter and settings, for cases when SFDP parser fails. The SFDP parser receives a Stack allocated copy of nor->params, called sfdp_params, and uses it to retrieve the serial flash discoverable parameters. JESD216 SFDP is a standard and has a higher priority than the default initialized flash parameters, so will overwrite the sfdp_params data when needed. All SFDP code uses the local copy of nor->params, that will overwrite it in the end, if the parser succeds. Saving and restoring the nor->params.erase_map is no longer needed, since the SFDP code does not touch it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Drop quad_enable() from 'struct spi-nor'Tudor Ambarus1-17/+23
All flash parameters and settings should reside inside 'struct spi_nor_flash_parameter'. Drop the local copy of quad_enable() and use the one from 'struct spi_nor_flash_parameter'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Use nor->paramsTudor Ambarus1-27/+19
The Flash parameters and settings are now stored in 'struct spi_nor'. Use this instead of the stack allocated params. Few functions stop passing pointer to params, as they can get it from 'struct spi_nor'. spi_nor_parse_sfdp() and children will keep passing pointer to params because of the roll-back mechanism: in case the parsing of SFDP fails, the legacy flash parameter and settings will be restored. Zeroing params is no longer needed because all SPI NOR users kzalloc 'struct spi_nor'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28mtd: spi-nor: Regroup flash parameter and settingsTudor Ambarus1-65/+0
The scope is to move all [FLASH-SPECIFIC] parameters and settings from 'struct spi_nor' to 'struct spi_nor_flash_parameter'. 'struct spi_nor_flash_parameter' describes the hardware capabilities and associated settings of the SPI NOR flash memory. It includes legacy flash parameters and settings that can be overwritten by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 Serial Flash Discoverable Parameters (SFDP) tables. All SFDP params and settings will fit inside 'struct spi_nor_flash_parameter'. Move spi_nor_hwcaps related code to avoid forward declarations. Add a forward declaration that we can't avoid: 'struct spi_nor' will be used in 'struct spi_nor_flash_parameter'. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-08-28Merge tag 'v5.3-rc6' into spi-nor/nextTudor Ambarus1-2/+3
Linux 5.3-rc6 Merge back latest release candidate, to include a fix that we depend on for new development: 834de5c1aa76 ("mtd: spi-nor: Fix the disabling of write protection at init")
2019-08-21mtd: spi-nor: intel-spi: Whitelist 4B read commandsAlexander Sverdlin1-0/+2
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes. Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports Flash chips up to 64Mbytes. D-1500 Integrated PCH documenation however has inconsistencies regarding FADDR register width and says nothing about particular commands issued to support 64Mbytes of Flash. Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and read operations work just fine after SPINOR_OP_READ_4B and SPINOR_OP_READ_FAST_4B are white-listed (currently only SPINOR_OP_READ_FAST_4B is used and only for Macronix). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-21mtd: spi-nor: fix a memory leak bugWenwen Wang1-1/+1
In spi_nor_parse_4bait(), 'dwords' is allocated through kmalloc(). However, it is not deallocated in the following execution if spi_nor_read_sfdp() fails, leading to a memory leak. To fix this issue, free 'dwords' before returning the error. Fixes: 816873eaeec6 ("mtd: spi-nor: parse SFDP 4-byte Address Instruction Table") Signed-off-by: Wenwen Wang <wenwen@cs.uga.edu> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-21mtd: spi-nor: Fix an error code in spi_nor_read_raw()Dan Carpenter1-2/+2
The problem is that if "ret" is negative then when we check if "ret > len", that condition is going to be true because of type promotion. So this patch re-orders the code to check for negatives first and preserve those error codes. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-21mtd: spi-nor: Fix Cadence QSPI RCU Schedule StallThor Thayer1-14/+5
The current Cadence QSPI driver sometimes caused a "rcu_sched self-detected stall" while writing large files. Stall Report: '# mtd_debug write /dev/mtd1 0 48816464 blob.img [ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU [ 1815.459789] rcu: 0-....: (2099 ticks this GP) idle=8c6/1/0x40000002 softirq=6492/6492 fqs=935 [ 1815.468442] rcu: (t=2100 jiffies g=8749 q=247) <snip> (abbreviated backtrace) [ 1815.772086] [<c05a3ea0>] (cqspi_exec_flash_cmd) (cqspi_read_reg) [ 1815.786203] [<c05a5488>] (cqspi_read_reg) from (read_sr) [ 1815.803790] [<c05a0330>] (read_sr) from (spi_nor_wait_till_ready_with_timeout) [ 1815.816610] [<c05a182c>] (spi_nor_wait_till_ready_with_timeout) from (spi_nor_write+0x104/0x1d0) [ 1815.836791] [<c05a1a44>] (spi_nor_write) from (part_write+0x50/0x58) <snip> [ 1815.997961] cadence-qspi ff809000.spi: Flash command execution timed out. [ 1816.004733] error -110 reading SR file_to_flash: write, size 0x2e8e150, n 0x2e8e150 write(): Connection timed out This was caused by a tight loop in cqspi_wait_for_bit(). Fix by using readl_relaxed_poll_timeout() which sleeps 10us while polling a register. Fit onto 80 character line by truncating the bool clear parameter Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20mtd: spi-nor : Remove SPI_NOR_HAS_TB flag on s25fl512sJungseung Lee1-1/+1
Currently, the Top/Bottom protection function (SPI_NOR_HAS_TB) is implemented to fit some flashes with TB bit on SR. s25fl512s has TBPROT bit on CR1, so the TB protection is not working on it. Fix the wrong flag on s25fl512s. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake SPI serial flashMika Westerberg1-0/+1
Intel Tiger Lake has the same SPI serial flash controller as Ice Lake. Add Tiger Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20mtd: spi-nor: add support for sst26wf016b memory ICEugeniy Paltsev1-0/+2
This commit adds support for the SST sst26wf016b flash memory IC. This IC was tested with "snps,dw-apb-ssi" SPI controller. We don't test dual/quad reads however sst26wf016b flash's datasheet advertises both dual and quad reads (and support of corresponding commands) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-20mtd: spi-nor: Add Winbond w25q256jvmAvi Fishman1-0/+2
Similar to w25q256 (besides not supporting QPI mode) but with different ID. The "JVM" suffix is in the datasheet. The datasheet indicates DUAL and QUAD are supported. https://www.winbond.com/resource-files/w25q256jv%20spi%20revi%2010232018%20plus.pdf Signed-off-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-08-13mtd: spi-nor: Fix the disabling of write protection at initTudor Ambarus1-2/+3
spi_nor_spansion_clear_sr_bp() depends on spansion_quad_enable(). While spansion_quad_enable() is selected as default when initializing the flash parameters, the nor->quad_enable() method can be overwritten later on when parsing BFPT. Select the write protection disable mechanism at spi_nor_init() time, when the nor->quad_enable() method is already known. Fixes: 191f5c2ed4b6faba ("mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-08-12mtd: spi-nor: Rework hwcaps selection for the spi-mem caseBoris Brezillon1-36/+147
The spi-mem layer provides a spi_mem_supports_op() function to check whether a specific operation is supported by the controller or not. This is much more accurate than the hwcaps selection logic based on SPI_{RX,TX}_ flags. Rework the hwcaps selection logic to use spi_mem_supports_op() when nor->spimem != NULL. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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