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2025-01-26Merge tag 'mtd/for-6.14' of ↵Linus Torvalds6-19/+37
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD changes: - There's been no major core change, just a bunch of driver related improvements. Amongst them the conversion to of_property_present() for non-boolean properties, the addition of the support for Fujitsu MB85RS128TY FRAM, a couple of improvements to the phram driver and the usual load of misc changes. Raw NAND changes: - A new controller driver, from Nuvoton, has been merged - Bastien Curutchet has contributed a series improving the Davinci controller driver, both on the organization of the code, but also on the performance side. The binding has also been converted to yaml, received a new OOB layout and now supports on-die ECC engines - The Qualcomm controller driver has been deeply cleaned to extract some parts of the code into a shared file with the Qualcomm SPI memory controller - Aside from these main changes, the Cadence binding has been converted to yaml, the brcmnand controller driver has received a small fix, otherwise some more minor changes have also made their way in SPI NAND changes: - The SPI NAND subsystem has seen a great improvement, with the advent of DTR operations (DDR operations, which may be extended to the address cycles). The first vendor driver to benefit from these improvements is the Winbond driver - A new manufacturer driver is added SkyHigh, with a new constraint for the core, it is impossible to disable the on-die ECC engine - A Foresee device is also now supported SPI NOR changes: - Several flash entries have been added: Atmel AT25SF321, Spansion S28HL256T and S28HL02GT - Support for vcc-supply regulators and their DT bindings has been added - The mx25u25635f entry has been dropped. The flash shares its ID with mx25u25645g and both parts have an SFDP table. Removing their entry lets them be driven by the generic SFDP-based driver" * tag 'mtd/for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (47 commits) mtd: spinand: skyhigh: Align with recent read from cache variant changes mtd: spinand: winbond: Add support for DTR operations mtd: spinand: winbond: Add comment about naming mtd: spinand: winbond: Update the *JW chip definitions mtd: spinand: Add support for read DTR operations mtd: spinand: Enhance the logic when picking a variant mtd: spinand: Add an optional frequency to read from cache macros mtd: spinand: Create distinct fast and slow read from cache variants mtd: hyperbus: Use of_property_present() for non-boolean properties mtd: st_spi_fsm: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr() mtd: rawnand: davinci: add ROM supported OOB layout mtd: spi-nor: sysfs: constify 'struct bin_attribute' mtd: spi-nor: spansion: Add support for S28HL02GT mtd: spi-nor: spansion: Add support for S28HL256T mtd: spi-nor: extend description of size member of struct flash_info mtd: rawnand: davinci: Reduce polling interval in NAND_OP_WAITRDY_INSTR mtd: rawnand: qcom: Fix build issue on x86 architecture mtd: rawnand: qcom: use FIELD_PREP and GENMASK mtd: nand: Add qpic_common API file mtd: rawnand: qcom: Add qcom prefix to common api ...
2025-01-15Revert "mtd: spi-nor: core: replace dummy buswidth from addr to data"Pratyush Yadav1-1/+1
This reverts commit 98d1fb94ce75f39febd456d6d3cbbe58b6678795. The commit uses data nbits instead of addr nbits for dummy phase. This causes a regression for all boards where spi-tx-bus-width is smaller than spi-rx-bus-width. It is a common pattern for boards to have spi-tx-bus-width == 1 and spi-rx-bus-width > 1. The regression causes all reads with a dummy phase to become unavailable for such boards, leading to a usually slower 0-dummy-cycle read being selected. Most controllers' supports_op hooks call spi_mem_default_supports_op(). In spi_mem_default_supports_op(), spi_mem_check_buswidth() is called to check if the buswidths for the op can actually be supported by the board's wiring. This wiring information comes from (among other things) the spi-{tx,rx}-bus-width DT properties. Based on these properties, SPI_TX_* or SPI_RX_* flags are set by of_spi_parse_dt(). spi_mem_check_buswidth() then uses these flags to make the decision whether an op can be supported by the board's wiring (in a way, indirectly checking against spi-{rx,tx}-bus-width). Now the tricky bit here is that spi_mem_check_buswidth() does: if (op->dummy.nbytes && spi_check_buswidth_req(mem, op->dummy.buswidth, true)) return false; The true argument to spi_check_buswidth_req() means the op is treated as a TX op. For a board that has say 1-bit TX and 4-bit RX, a 4-bit dummy TX is considered as unsupported, and the op gets rejected. The commit being reverted uses the data buswidth for dummy buswidth. So for reads, the RX buswidth gets used for the dummy phase, uncovering this issue. In reality, a dummy phase is neither RX nor TX. As the name suggests, these are just dummy cycles that send or receive no data, and thus don't really need to have any buswidth at all. Ideally, dummy phases should not be checked against the board's wiring capabilities at all, and should only be sanity-checked for having a sane buswidth value. Since we are now at rc7 and such a change might introduce many unexpected bugs, revert the commit for now. It can be sent out later along with the spi_mem_check_buswidth() fix. Fixes: 98d1fb94ce75 ("mtd: spi-nor: core: replace dummy buswidth from addr to data") Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com> Closes: https://lore.kernel.org/linux-mtd/3342163.44csPzL39Z@steina-w/ Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-01-13mtd: spi-nor: sysfs: constify 'struct bin_attribute'Thomas Weißschuh1-4/+4
The sysfs core now allows instances of 'struct bin_attribute' to be moved into read-only memory. Make use of that to protect them against accidental or malicious modifications. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241222-sysfs-const-bin_attr-mtd-v1-1-ee13140a4e9b@weissschuh.net
2025-01-13mtd: spi-nor: spansion: Add support for S28HL02GTTakahiro Kuwano1-0/+5
Infineon S28HL02GT is 3.0V, 2Gb Flash device with Octal interface. It has the same functionalities with S28HS02GT. Link: https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> [pratyush@kernel.org: add comment with flash name] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/dc6aa706253a5200ff0c0d4523c2540312575c01.1734588106.git.Takahiro.Kuwano@infineon.com
2025-01-13mtd: spi-nor: spansion: Add support for S28HL256TTakahiro Kuwano1-0/+5
Infineon S28HL256T is 3.0V, 256Mb Flash device with Octal interface. It has the same functionalities with S28HS256T(1.8V). Link: https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> [pratyush@kernel.org: add comment with flash name] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/f052b04693f1100e725e076fd8a0ae339f8002c4.1734588106.git.Takahiro.Kuwano@infineon.com
2025-01-13mtd: spi-nor: extend description of size member of struct flash_infoTudor Ambarus1-1/+5
We use the size as an indicator whether to parse SFDP or not. We don't introduce a dedicated member for SFDP parsing because we'd like to keep the struct size at a minimum, as it's used for every flash declaration. Ideally we won't have flash entries at all, but there are still flash parameters that aren't defined by SFDP, thus we need to statically specify them. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241219-spi-nor-flash-info-size-desc-v1-1-6b53cf011027@linaro.org
2024-12-06mtd: spi-nor: macronix: remove mx25u25635f from parts list to enable SFDPParth Pancholi1-6/+0
The Macronix mx25u25635f flash device supports SFDP initialization. This commit removes the specific mx25u25635f entry (NOR ID 0xc22539), along with its size and flags, from the NOR parts list. By removing this entry, both mx25u25635f and mx25u25645g (which share the same NOR ID) will utilize the generic flash driver configuration. This change allows both devices (mx25u25635f and mx25u25645g) to leverage SFDP-defined parameters, enabling dual and quad read operations without the need for manual adjustment of no_sfdp_flags. Link: https://www.macronix.com/Lists/Datasheet/Attachments/8663/MX25U25635F,%201.8V,%20256Mb,%20v1.5.pdf Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241105105844.257676-1-parth105105@gmail.com
2024-12-06mtd: spi-nor: support vcc-supply regulatorPeng Fan1-0/+5
SPI NOR flashes needs power supply to work properly. The power supply maybe software controllable per board design. So add the support for an vcc-supply regulator. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> [ta: move devm_regulator_get_enable() to spi_nor_probe().] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111111946.9048-3-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: use local variable for struct deviceTudor Ambarus1-7/+7
Use a local variable for the struct device pointers to avoid dereferencing. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111111946.9048-2-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: macronix: use nor->addr_nbytesTudor Ambarus1-1/+2
Use the nor->addr_nbytes set by the core, we shouldn't use magic numbers or states that are not tracked by the core. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Acked-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111113609.12093-1-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: atmel: add at25sf321 entryMarcus Folkesson1-0/+4
Add entry for the at25sf321 32Mbit SPI flash. This flash is populated on a custom board and was tested at 10MHz frequency using the "ti,da830-spi" SPI controller. Link: https://www.renesas.com/en/document/dst/at25sf321-datasheet?r=1608801 Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241116-spi-nor-v4-1-3de8ac6fd0be@gmail.com
2024-11-29Merge tag 'driver-core-6.13-rc1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is a small set of driver core changes for 6.13-rc1. Nothing major for this merge cycle, except for the two simple merge conflicts are here just to make life interesting. Included in here are: - sysfs core changes and preparations for more sysfs api cleanups that can come through all driver trees after -rc1 is out - fw_devlink fixes based on many reports and debugging sessions - list_for_each_reverse() removal, no one was using it! - last-minute seq_printf() format string bug found and fixed in many drivers all at once. - minor bugfixes and changes full details in the shortlog" * tag 'driver-core-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (35 commits) Fix a potential abuse of seq_printf() format string in drivers cpu: Remove spurious NULL in attribute_group definition s390/con3215: Remove spurious NULL in attribute_group definition perf: arm-ni: Remove spurious NULL in attribute_group definition driver core: Constify bin_attribute definitions sysfs: attribute_group: allow registration of const bin_attribute firmware_loader: Fix possible resource leak in fw_log_firmware_info() drivers: core: fw_devlink: Fix excess parameter description in docstring driver core: class: Correct WARN() message in APIs class_(for_each|find)_device() cacheinfo: Use of_property_present() for non-boolean properties cdx: Fix cdx_mmap_resource() after constifying attr in ->mmap() drivers: core: fw_devlink: Make the error message a bit more useful phy: tegra: xusb: Set fwnode for xusb port devices drm: display: Set fwnode for aux bus devices driver core: fw_devlink: Stop trying to optimize cycle detection logic driver core: Constify attribute arguments of binary attributes sysfs: bin_attribute: add const read/write callback variants sysfs: implement all BIN_ATTR_* macros in terms of __BIN_ATTR() sysfs: treewide: constify attribute callback of bin_attribute::llseek() sysfs: treewide: constify attribute callback of bin_attribute::mmap() ...
2024-11-19Merge tag 'spi-nor/for-6.13' of ↵Miquel Raynal7-2/+110
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary when configured in Octal DTR mode. For such cases the byte order is propagated through SPI MEM to the SPI controllers so that the controllers swap the bytes back at runtime. This avoids breaking the boot sequence because of the endianness problems that appear when the bootloaders use 1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the SPI MEM byte swap support we queue a patch for the SPI MXIC controller that swaps the bytes back at runtime. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAmczG/oACgkQS1VPR6WN # FOnTCAf/YjH9AimQAFJLRKoGqsf6boh1JppcRh1YTRS+D6+Ap9+s1gJoZZYs5VWA # vNfBzGqDXknBvpmOgoXnuDu2zFs9FUvdN5Kf7w6LiS5qtz7uOxHdVoDQyDgnN6w5 # 9ts7qF7LViBHg/HgTEzQT2Zj6qmvIwUbccIkmJeehWjEP/urzOML5nPnM9g4HZVB # W8B5KQ4TiOY1GxkXvIP6EQS6mDKznP3yl2Hnsmk0HPpSm6D807O2zvT+z1SCxpjy # C8+mYRKsRxHoFGL6UzWgqREGBn2wzF7Ral1CR9SpSZZLLtr6S0shqRzKiiH8eiZK # 1hFpXzMS3OWi4a/5724AWaqcR0Qgqw== # =jf3Q # -----END PGP SIGNATURE----- # gpg: Signature made Tue 12 Nov 2024 10:12:26 AM CET # gpg: using RSA key 1D422ACACF0EC86D5E1DFEDF4B554F47A58D14E9 # gpg: Good signature from "Tudor Ambarus (4096-bit rsa key) <tudor.ambarus@microchip.com>" [full] # gpg: aka "Tudor Ambarus <tudor.ambarus@gmail.com>" [full] # gpg: tudor.ambarus@microchip.com: Verified 15 signatures in the past 5 years. # Encrypted 0 messages. # gpg: tudor.ambarus@gmail.com: Verified 15 signatures in the past 5 years. # Encrypted 0 messages.
2024-11-12mtd: spi-nor: core: replace dummy buswidth from addr to dataCheng Ming Lin1-1/+1
The default dummy cycle for Macronix SPI NOR flash in Octal Output Read Mode(1-1-8) is 20. Currently, the dummy buswidth is set according to the address bus width. In the 1-1-8 mode, this means the dummy buswidth is 1. When converting dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the host to read data 4 cycles too early. Since the protocol data buswidth is always greater than or equal to the address buswidth. Setting the dummy buswidth to match the data buswidth increases the likelihood that the dummy cycle-to-byte conversion will be divisible, preventing the host from reading data prematurely. Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Cc: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Link: https://lore.kernel.org/r/20241112075242.174010-2-linchengming884@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-11-11mtd: spi-nor: winbond: add "w/ and w/o SFDP" commentTudor Ambarus1-0/+1
Commit d35df77707bf ("mtd: spi-nor: winbond: fix w25q128 regression") upstream fixed a regression for flavors of 0xef4018 flash that don't define SFDP tables. Add a comment on the flash definition highlighting that there are flavors of flashes with and without SFDP support. It spares developers searching the entire git log for when we'll better handle these cases. Acked-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241029080049.96679-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-11-05sysfs: treewide: constify attribute callback of bin_is_visible()Thomas Weißschuh1-1/+1
The is_bin_visible() callbacks should not modify the struct bin_attribute passed as argument. Enforce this by marking the argument as const. As there are not many callback implementers perform this change throughout the tree at once. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Acked-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Krzysztof Wilczyński <kw@linux.com> Link: https://lore.kernel.org/r/20241103-sysfs-const-bin_attr-v2-5-71110628844c@weissschuh.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-10-29mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in RD_ANY_REG_OPTakahiro Kuwano1-0/+1
In octal DTR mode, RD_ANY_REG_OP needs to use 4-byte address regardless of flash's internal address mode. Use nor->addr_nbytes which is set to 4 during setup. Fixes: eff9604390d6 ("mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20241016000837.17951-1-Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-21mtd: Switch back to struct platform_driver::remove()Uwe Kleine-König2-2/+2
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/mtd to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20241007205803.444994-10-u.kleine-koenig@baylibre.com
2024-10-04mtd: spi-nor: add support for Macronix Octal flashAlvinZhou1-1/+8
Add manufacturer ID 0xc2 at the end of ID table to allow manufacturer fixups to be applied for any Macronix flash. This spares us of adding new flash entries for flashes that can be initialized solely based on the SFDP data, but still need the manufacturer hooks to set parameters that can't be discovered at SFDP parsing time. The ID is added in order to set the octal DTR methods. SFDP defines a "Command Sequences to Change to Octal DDR (8D-8D-8D) Mode" which can enable the octal DTR mode. Until that is parsed and used, use the local defined method. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-7-alvinzhou.tw@gmail.com [ta: update commit message and comment in the code] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPTTudor Ambarus2-0/+5
Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. This info flag will be used as a basis to determine whether there is byte swapping of data for SPI NOR flash in octal DTR mode. The controller driver will check whether byte swapping is supported to determine whether the corresponding operation are supported, thus avoiding the generation of unexpected data order. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-5-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: core: Allow specifying the byte order in Octal DTR modeTudor Ambarus2-0/+4
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controller is not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that it comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-4-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: add Octal DTR support for Macronix flashAlvinZhou1-0/+90
Create Macronix specify method for enable Octal DTR mode and set 20 dummy cycles to allow running at the maximum supported frequency for Macronix Octal flash. Use number of dummy cycles which is parse by SFDP then convert it to bit pattern and set in CR2 register. Set CR2 register for enable octal DTR mode. Use Read ID to confirm that enabling/disabling octal DTR mode was successful. Macronix ID format is A-A-B-B-C-C in octal DTR mode. To ensure the successful enablement of octal DTR mode, confirm that the 6-byte data is entirely correct. Co-developed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-2-alvinzhou.tw@gmail.com
2024-09-14mtd: spi-nor: fix flash probingMichael Walle1-1/+2
Fix flash probing by name. Flash entries without a name are allowed since commit 15eb8303bb42 ("mtd: spi-nor: mark the flash name as obsolete"). But it was just until recently that a flash entry without a name was actually introduced. This triggers a bug in the legacy probe by name path. Skip entries without a name to fix it. Fixes: 2095e7da8049 ("mtd: spi-nor: spansion: Add support for S28HS256T") Reported-by: Jon Hunter <jonathanh@nvidia.com> Closes: https://lore.kernel.org/r/66c8ebb0-1324-4ad9-9926-8d4eb7e1e63a@nvidia.com/ Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240909072854.812206-1-mwalle@kernel.org
2024-09-14mtd: spi-nor: spansion: Add support for S28HS256TTakahiro Kuwano1-0/+4
Infineon S28HS256T is 256Mb Octal SPI device which has same functionalities with 512Mb and 1Gb parts. Link: https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240830080428.6994-1-Takahiro.Kuwano@infineon.com
2024-09-14mtd: spi-nor: winbond: add Zetta ZD25Q128C supportMichael Walle1-0/+26
Zetta normally uses BAh as its vendor ID. But for the ZD25Q128C they took the one from Winbond and messed up the size parameters in SFDP. Most functions seem compatible with the W25Q128, we just have to fix up the size. Link: http://www.zettadevice.com/upload/file/20150821/DS_Zetta_25Q128_RevA.pdf Link: https://www.lcsc.com/datasheet/lcsc_datasheet_2312081757_Zetta-ZD25Q128CSIGT_C19626875.pdf Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240804221535.291923-1-mwalle@kernel.org
2024-09-14mtd: spi-nor: micron-st: Add n25q064a WP supportBrian Norris1-0/+2
These flash chips are used on Google / TP-Link / ASUS OnHub devices, and OnHub devices are write-protected by default (same as any other ChromeOS/Chromebook system). I've referred to datasheets, and tested on OnHub devices. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240726185825.142733-1-computersforpeace@gmail.com
2024-09-14mtd: spi-nor: sst: Factor out common write operation to `sst_nor_write_data()`Csókás, Bence1-20/+19
Writing to the Flash in `sst_nor_write()` is a 3-step process: first an optional one-byte write to get 2-byte-aligned, then the bulk of the data is written out in vendor-specific 2-byte writes. Finally, if there's a byte left over, another one-byte write. This was implemented 3 times in the body of `sst_nor_write()`. To reduce code duplication, factor out these sub-steps to their own function. Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: fixup whitespace, use %zu instead of %i in WARN()] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240710091401.1282824-1-csokas.bence@prolan.hu
2024-06-21mtd: spi-nor: winbond: fix w25q128 regressionMichael Walle1-0/+2
Commit 83e824a4a595 ("mtd: spi-nor: Correct flags for Winbond w25q128") removed the flags for non-SFDP devices. It was assumed that it wasn't in use anymore. This wasn't true. Add the no_sfdp_flags as well as the size again. We add the additional flags for dual and quad read because they have been reported to work properly by Hartmut using both older and newer versions of this flash, the similar flashes with 64Mbit and 256Mbit already have these flags and because it will (luckily) trigger our legacy SFDP parsing, so newer versions with SFDP support will still get the parameters from the SFDP tables. Reported-by: Hartmut Birr <e9hack@gmail.com> Closes: https://lore.kernel.org/r/CALxbwRo_-9CaJmt7r7ELgu+vOcgk=xZcGHobnKf=oT2=u4d4aA@mail.gmail.com/ Fixes: 83e824a4a595 ("mtd: spi-nor: Correct flags for Winbond w25q128") Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Esben Haabendal <esben@geanix.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240621120929.2670185-1-mwalle@kernel.org
2024-06-18mtd: spi-nor: simplify spi_nor_get_flash_info()Michael Walle1-18/+14
Rework spi_nor_get_flash_info() to make it look more straight forward and esp. don't return early. The latter is a preparation to check for deprecated flashes. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240603134055.1859863-1-mwalle@kernel.org
2024-05-27mtd: spi-nor: get rid of SPI_NOR_NO_FRMichael Walle3-13/+17
The Everspin FRAM devices are the only user of the NO_FR flag. Drop the global flag and instead use a manufacturer fixup for the Everspin flashes to drop the fast read support. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: s/evervision/everspin/g in code and commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-5-mwalle@kernel.org
2024-05-27mtd: spi-nor: remove .setup() callbackMichael Walle2-65/+45
With the removal of the Xilinx flashes, there is no more flash driver using that hook. The original intention was to let the driver configure special requirements like page size an opcodes. This is already possible by other means and it is unlikely a flash will overwrite the (more or less complex) setup function. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-4-mwalle@kernel.org
2024-05-27mtd: spi-nor: get rid of non-power-of-2 page size handlingMichael Walle2-34/+11
The Xilinx flashes were the only users of page sizes that were not power of 2. Support for them has been dropped, thus we can also get rid of the special page size handling for it. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: fixup minor typos and grammar in commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-3-mwalle@kernel.org
2024-05-27mtd: spi-nor: Remove support for Xilinx S3AN flashesMichael Walle4-172/+0
These flashes are kind of an oddball for the very old Xilinx Spartan 3 FPGAs to store their bitstream. More importantly, they reuse the Atmel JEDEC manufacturer ID and in fact the at45db081d already blocks the use of the 3S700AN flash chip. It's time to sunset support for these flashes. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Cc: Ricardo Ribalda <ribalda@kernel.org> Acked-by: Ricardo Ribalda <ribalda@chromium.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-2-mwalle@kernel.org
2024-04-29mtd: spi-nor: replace unnecessary div64_u64() with div_u64()Michael Walle1-2/+2
Both occurrences of div64_u64() just have a u8 or u32 divisor. Use div_u64() instead. Many 32 bit architectures can optimize this variant better than a full 64 bit divide. Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/9ba7f4e6-2b8b-44a3-9cac-9ed6e50f1700@moroto.mountain/ Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: touched up commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240429121113.803703-1-mwalle@kernel.org
2024-03-14mtd: spi-nor: core: correct type of iMuhammad Usama Anjum1-1/+1
The i should be signed to find out the end of the loop. Otherwise, i >= 0 is always true and loop becomes infinite. Make its type to be int. Fixes: 6a9eda34418f ("mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase map") Signed-off-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240304090103.818092-1-usama.anjum@collabora.com
2024-02-26mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase mapTakahiro Kuwano1-2/+56
Some of Infineon SPI NOR flash devices support hybrid sector layout that overlays 4KB sectors on a 256KB sector and SPI NOR framework recognizes that by parsing SMPT and construct params->erase_map. The hybrid sector layout is similar to CFI flash devices that have small sectors on top and/or bottom address. In case of CFI flash devices, the erase map information is parsed through CFI table and populated into mtd->eraseregions so that users can create MTD partitions that aligned with small sector boundaries. This patch provides the same capability to SPI NOR flash devices that have non-uniform erase map. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/35d0962986e493b06c13bdf7ada8130a9966dc02.1708404584.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-02-26mtd: spi-nor: core: get rid of SNOR_OVERLAID_REGION flagTakahiro Kuwano4-17/+8
Only SNOR_OVERLAID_REGION is defined for flags in the spi_nor_erase_region structure. It can be replaced by a boolean parameter. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/076416d5dc8328dec72d31db12b9bec96bf0ac66.1708404584.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-02-26mtd: spi-nor: core: get rid of SNOR_LAST_REGION flagTakahiro Kuwano4-105/+41
Introduce n_regions in spi_nor_erase_map structure and remove SNOR_LAST_REGION flag. Loop logics that depend on the flag are also reworked to use n_regions as loop condition. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Suggested-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/eded84294bd81e966d6f423e578fc2cfb9a4a5b6.1708404584.git.Takahiro.Kuwano@infineon.com [ta: update spi_nor_init_erase_cmd_list() and break the for loop sooner.] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-02-26mtd: spi-nor: core: rework struct spi_nor_erase_regionTakahiro Kuwano4-67/+46
Encoding bitmask flags into offset worsen the code readability. The erase type mask and flags should be stored in dedicated members. Also, erase_map.uniform_erase_type can be removed as it is redundant. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Suggested-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/8e5e9e4081ed9f16ea9dce30693304a4b54d19b1.1708404584.git.Takahiro.Kuwano@infineon.com [ta: remove spi_nor_region_end()] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-01-10Merge tag 'mtd/for-6.8' of ↵Linus Torvalds11-119/+227
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD: - Apart from preventing the mtdblk to run on top of ftl or ubiblk (which may cause security issues and has no meaning anyway), there are a few misc fixes. Raw NAND: - Two meaningful changes this time. The conversion of the brcmnand driver to the ->exec_op() API, this series brought additional changes to the core in order to help controller drivers to handle themselves the WP pin during destructive operations when relevant. - There is also a series bringing important fixes to the sequential read feature. - As always, there is as well a whole bunch of miscellaneous W=1 fixes, together with a few runtime fixes (double free, timeout value, OOB layout, missing register initialization) and the usual load of remove callbacks turned into void (which led to switch the txx9ndfmc driver to use module_platform_driver()). SPI NOR: - SPI NOR comes with die erase support for multi die flashes, with new octal protocols (1-1-8 and 1-8-8) parsed from SFDP and with an updated documentation about what the contributors shall consider when proposing flash additions or updates. - Michael Walle stepped out from the reviewer role to maintainer" * tag 'mtd/for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (39 commits) mtd: rawnand: Clarify conditions to enable continuous reads mtd: rawnand: Prevent sequential reads with on-die ECC engines mtd: rawnand: Fix core interference with sequential reads mtd: rawnand: Prevent crossing LUN boundaries during sequential reads mtd: Fix gluebi NULL pointer dereference caused by ftl notifier dt-bindings: mtd: partitions: u-boot: Fix typo mtd: rawnand: s3c2410: fix Excess struct member description kernel-doc warnings MAINTAINERS: change my mail to the kernel.org one mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 protocol from SFDP mtd: spi-nor: drop superfluous debug prints mtd: spi-nor: sysfs: hide the flash name if not set mtd: spi-nor: mark the flash name as obsolete mtd: spi-nor: print flash ID instead of name mtd: maps: vmu-flash: Fix the (mtd core) switch to ref counters mtd: ssfdc: Remove an unused variable mtd: rawnand: diskonchip: fix a potential double free in doc_probe mtd: rawnand: rockchip: Add missing title to a kernel doc comment mtd: rawnand: rockchip: Rename a structure mtd: rawnand: pl353: Fix kernel doc mtd: spi-nor: micron-st: Add support for mt25qu01g ...
2023-12-20mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 protocol from SFDPJaimeLiao2-0/+36
BFPT 17th DWORD contains the information about 1-1-8 and 1-8-8. Parse BFPT DWORD[17] instruction to determine whether flash supports 1-1-8 and 1-8-8, and set its dummy cycles accordingly. Validated only the 1-1-8 read using a macronix flash with Xilinx board zynq-picozed. Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20231219102103.92738-2-jaimeliao.tw@gmail.com [ta: update commit message, get rid of extra dereference] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-19mtd: spi-nor: drop superfluous debug printsTudor Ambarus1-18/+0
The mtd data shall be obtained with the mtd ioctls or with new debugfs entries if one cares. Drop the debug prints. Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20231215082138.16063-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-19mtd: spi-nor: sysfs: hide the flash name if not setJaimeLiao1-0/+2
The flash name is not reliable as we saw flash ID collisions. Hide the flash name if not set. Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Reviewed-by: Michael Walle <michael@walle.cc> [ta: update commit subject and description and the sysfs description] Link: https://lore.kernel.org/r/20231215082138.16063-4-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-19mtd: spi-nor: mark the flash name as obsoleteTudor Ambarus1-1/+1
The flash name is unreliable as we saw flash ID collisions. Mark the name as obsolete. Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20231215082138.16063-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-19mtd: spi-nor: print flash ID instead of nameTudor Ambarus1-2/+2
We saw flash ID collisions which make the flash name unreliable. Print the manufacturer and device ID instead of the flash name. Lower the print to dev_dbg to stop polluting the kernel log. Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20231215082138.16063-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-06mtd: spi-nor: micron-st: Add support for mt25qu01gFabio Estevam1-0/+25
Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory model. Link: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf Signed-off-by: Fabio Estevam <festevam@denx.de> [ta: introduce die erase] Link: https://lore.kernel.org/r/20231125123529.55686-6-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-06mtd: spi-nor: remove NO_CHIP_ERASE flagTudor Ambarus2-8/+3
There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Tested-by: Fabio Estevam <festevam@denx.de> Link: https://lore.kernel.org/r/20231125123529.55686-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-06mtd: spi-nor: micron-st: enable die erase for multi die flashesTudor Ambarus2-19/+47
Enable die erase for multi die flashes, it will speed the erase time. Unfortunately, Micron does not provide a 4-byte opcode equivalent for the die erase. The SFDP 4BAIT table fails to consider the die erase too, the standard can be improved. Thus we're forced to enter in the 4 byte address mode in order to benefit of the die erase. Tested on n25q00. This flash defines the 4BAIT SFDP table, thus it will use the 4BAIT opcodes for reads, page programs or erases, with the exception that it will use the die erase command in the 4 byte address mode. Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_1gb_3v_65nm.pdf?rev=b6eba74759984f749f8c039bc5bc47b7 Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf?rev=43f7f66fc8da4d7d901b35fa51284c8f Link: https://lore.kernel.org/r/20231125123529.55686-4-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-06mtd: spi-nor: spansion: enable die erase for multi die flashesTudor Ambarus1-2/+2
Enable die erase for spansion multi die flashes. Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20231125123529.55686-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-12-06mtd: spi-nor: add erase die (chip) capabilityTudor Ambarus3-37/+81
JESD216 mentions die erase, but does not provide an opcode for it. Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says: "Typical time to erase one chip (die). User must poll device busy to determine if the operation has completed. For a device consisting of multiple dies, that are individually accessed, the time is for each die to which a chip erase command is applied." So when a flash consists of a single die, this is the erase time for the full chip (die) erase, and when it consists of multiple dies, it's the die erase time. Chip and die are the same thing. Add support for die erase. For now, benefit of the die erase when addr and len are aligned with die size. This could be improved however for the uniform and non-uniform erases cases to use the die erase when possible. For example if one requests that an erase of a 2 die device starting from the last 64KB of the first die to the end of the flash size, we could use just 2 commands, a 64KB erase and a die erase. This improvement is left as an exercise for the reader. Tested-by: Fabio Estevam <festevam@denx.de> Link: https://lore.kernel.org/r/20231125123529.55686-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-18 01:50:33 +0300