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2020-03-11mtd: rawnand: ams-delta: Make the driver custom I/O readyJanusz Krzysztofik1-6/+26
In order to be merged with "gpio-nand", the driver must support custom (non-GPIO) I/O accessors. Allow platforms to omit data GPIO port as well as NWE pin info from device setup. For the driver to still work on such platform, custom I/O accessors as well as a custom probe function which initialises the driver private structure with those accessors must be added to the driver. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-14-jmkrzyszt@gmail.com
2020-03-11mtd: rawnand: ams-delta: Drop useless local variableJanusz Krzysztofik1-5/+3
For consistency with adjacent code patterns used in the driver probe function, store data GPIO array pointer directly in a respective field of the driver private structure instead of storing it intermediately in a local variable for error checking. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-13-jmkrzyszt@gmail.com
2020-03-11mtd: rawnand: ams-delta: Support custom driver initialisationJanusz Krzysztofik1-0/+11
In preparation for extending the driver with custom I/O support, try to obtain device specific initialisation routine from a matching device table entry and run it as an additional step of device probe. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-12-jmkrzyszt@gmail.com
2020-03-11mtd: rawnand: ams-delta: Add module device tablesJanusz Krzysztofik1-0/+18
In preparation for merging the driver with "gpio-nand", introduce module device tables where new device models can be accommodated as soon as respective support is added. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-11-jmkrzyszt@gmail.com
2020-03-11mtd: fix spelling mistake "BlockMultiplerBits" -> "BlockMultiplierBits"Colin Ian King1-1/+1
There is a spelling mistake (missing i) in pr_info messages. Fix these. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200208113612.817988-1-colin.king@canonical.com
2020-03-09mtd: rawnand: ams-delta: Handle more GPIO pins as optionalJanusz Krzysztofik1-2/+4
In order to make the driver more useful on platforms other than Amstrad Delta, allow GPIO descriptor pointers of possibly non-critical NWP and NCE pins to be initialised as NULL. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-10-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Make read pulses optionalJanusz Krzysztofik1-3/+6
Allow platforms to omit NRE pin from device configuration by requesting that pin as optional. In that case, also don't apply read pulse width from chip SDR timings. There should be no need for further code adjustments as gpiolib can handle NULL GPIO descriptor pointers. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-9-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Don't hardcode read/write pulse widthsJanusz Krzysztofik1-2/+27
Instead of forcing Amstrad Delta specific read/write pulse widths, use variables initialised from respective fields of chip SDR timings. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-8-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Push inversion handling to gpiolibJanusz Krzysztofik1-11/+11
Let platforms take care of declaring correct GPIO pin polarity so we can just ask a GPIO line to be asserted or deasserted and gpiolib deals with the rest depending on how the platform is configured. Inspired by similar changes to regulator drivers by Linus Walleij <linus.walleij@linaro.org>, thanks! Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-7-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Enable OF partition info supportJanusz Krzysztofik1-0/+1
Provide MTD layer with device OF node info required by OF partition parser. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-6-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Drop board specific partition infoJanusz Krzysztofik1-27/+2
Now as we support fetching partition info from device platform data and the Amstrad Delta board file provides that info, drop it from the driver code. v2: rebase on top of gpio_nand_platdata extension Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-5-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Use struct gpio_nand_platdataJanusz Krzysztofik1-2/+10
In order to be able to move the hardcoded Amstrad Delta partition info from the driver code to the board file, reuse gpio_nand_platdata structure owned by "gpio-nand" driver and try to obtain information on device partitions from device platform data. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-3-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ams-delta: Write protect device during probeJanusz Krzysztofik1-2/+16
Initialise NWP GPIO pin as asserted to protect the device from hazard during setup of other GPIO pins. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200212003929.6682-2-jmkrzyszt@gmail.com
2020-03-09mtd: rawnand: ingenic: Use devm_platform_ioremap_resource()Paul Cercueil1-3/+1
Use devm_platform_ioremap_resource() instead of platform_get_resource() + devm_ioremap_resource(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200211173151.27587-1-paul@crapouillou.net
2020-03-09mtd: spinand: toshiba: Add comment about Kioxia IDYoshio Furuyama1-0/+1
Add a comment above NAND_MFR_TOSHIBA and SPINAND_MFR_TOSHIBA definitions that Toshiba and Kioxia ID are the same. Since its independence from Toshiba Group, Toshiba memory Co has become Kioxia Co. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1581051561-7302-1-git-send-email-ytc-mb-yfuruyama7@kioxia.com
2020-03-09mtd: rawnand: denali: deassert write protect pinMasahiro Yamada1-0/+1
If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200127123934.11847-1-yamada.masahiro@socionext.com
2020-03-09mtd: rawnand: free the nand_device objectChristophe Kerello1-0/+2
This patch releases the resources allocated in nanddev_init function. Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object") Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1579767768-32295-1-git-send-email-christophe.kerello@st.com
2020-03-09mtd: rawnand: Ensure nand_soft_waitrdy wait period is enoughMartin Devera1-1/+6
The used way to compute jiffies timeout brokes when jiffie difference is 1. Assume that nand_soft_waitrdy is called with timeout_ms==1. Jiffies are 1000 for example (assume something more like 1000.99 - just before incrementing to 1001). We compute timeout_ms = 1000+msecs_to_jiffies(1) = 1001. nand_read_data_op is called for the first time and returns 0. During the call jiffies changes to 1001 thus "while loop" ends here (wrongly). Notice that routine was called with expected timeout 1ms but actual timeout used was something between 0...1ms. Fixes STM32MP1 FMC2 NAND controller which sometimes failed exactly in this way. Signed-off-by: Martin Devera <devik@eaxlabs.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200116135431.17480-1-devik@eaxlabs.cz
2020-01-31Merge tag 'mtd/for-5.6' of ↵Linus Torvalds7-32/+83
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD core - block2mtd: page index should use pgoff_t - maps: physmap: minimal Runtime PM support - maps: pcmciamtd: avoid possible sleep-in-atomic-context bugs - concat: Fix a comment referring to an unknown symbol Raw NAND: - Macronix: Use match_string() helper - Atmel: switch to using devm_fwnode_gpiod_get() - Denali: rework the SKIP_BYTES feature and add reset controlling - Brcmnand: set appropriate DMA mask - Cadence: add unspecified HAS_IOMEM dependency - Various cleanup. Onenand: - Rename Samsung and Omap2 drivers to avoid possible build warnings - Enable compile testing - Various build issues - Kconfig cleanup SPI-NAND: - Support for Toshiba TC58CVG2S0HRAIJ SPI-NOR: - Add support for TB selection using SR bit 6, - Add support for few flashes" * tag 'mtd/for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (41 commits) mtd: concat: Fix a comment referring to an unknown symbol mtd: rawnand: add unspecified HAS_IOMEM dependency mtd: block2mtd: page index should use pgoff_t mtd: maps: physmap: Add minimal Runtime PM support mtd: maps: pcmciamtd: fix possible sleep-in-atomic-context bugs in pcmciamtd_set_vpp() mtd: onenand: Rename omap2 driver to avoid a build warning mtd: onenand: Use a better name for samsung driver mtd: rawnand: atmel: switch to using devm_fwnode_gpiod_get() mtd: spinand: add support for Toshiba TC58CVG2S0HRAIJ mtd: rawnand: macronix: Use match_string() helper to simplify the code mtd: sharpslpart: Fix unsigned comparison to zero mtd: onenand: Enable compile testing of OMAP and Samsung drivers mtd: onenand: samsung: Fix printing format for size_t on 64-bit mtd: onenand: samsung: Fix pointer cast -Wpointer-to-int-cast warnings on 64 bit mtd: rawnand: denali: remove hard-coded DENALI_DEFAULT_OOB_SKIP_BYTES mtd: rawnand: denali_dt: add reset controlling dt-bindings: mtd: denali_dt: document reset property mtd: rawnand: denali_dt: Add support for configuring SPARE_AREA_SKIP_BYTES mtd: rawnand: denali_dt: error out if platform has no associated data mtd: rawnand: brcmnand: Set appropriate DMA mask ...
2020-01-28Merge tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremapLinus Torvalds3-5/+5
Pull ioremap updates from Christoph Hellwig: "Remove the ioremap_nocache API (plus wrappers) that are always identical to ioremap" * tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap: remove ioremap_nocache and devm_ioremap_nocache MIPS: define ioremap_nocache to ioremap
2020-01-27Merge tag 'nand/for-5.6' into mtd/nextMiquel Raynal8-40/+124
Raw NAND * Macronix: Use match_string() helper * Atmel: switch to using devm_fwnode_gpiod_get() * Denali: rework the SKIP_BYTES feature and add reset controlling * Brcmnand: set appropriate DMA mask * Various cleanup. Onenand drivers * Rename Samsung and Omap2 drivers to avoid possible build warnings * Enable compile testing * Various build issues * Kconfig cleanup SPI-NAND * Support for Toshiba TC58CVG2S0HRAIJ
2020-01-27mtd: rawnand: add unspecified HAS_IOMEM dependencyBrendan Higgins1-1/+1
Currently CONFIG_MTD_NAND_CADENCE implicitly depends on CONFIG_HAS_IOMEM=y; consequently, on architectures without IOMEM we get the following build error: ld: drivers/mtd/nand/raw/cadence-nand-controller.o: in function `cadence_nand_dt_probe.cold.31': drivers/mtd/nand/raw/cadence-nand-controller.c:2969: undefined reference to `devm_platform_ioremap_resource' ld: drivers/mtd/nand/raw/cadence-nand-controller.c:2977: undefined reference to `devm_ioremap_resource' Fix the build error by adding the unspecified dependency. Reported-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: atmel: switch to using devm_fwnode_gpiod_get()Dmitry Torokhov1-10/+10
devm_fwnode_get_index_gpiod_from_child() is going away as the name is too unwieldy, let's switch to using the new devm_fwnode_gpiod_get(). Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: macronix: Use match_string() helper to simplify the codeYueHaibing1-7/+4
match_string() returns the array index of a matching string. Use it instead of the open-coded implementation. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: denali: remove hard-coded DENALI_DEFAULT_OOB_SKIP_BYTESMasahiro Yamada1-14/+7
As commit 0d55c668b218 (mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES register to 8 if unset") says, there were three solutions discussed: [1] Add a DT property to specify the skipped bytes in OOB [2] Associate the preferred value with compatible [3] Hard-code the default value in the driver At that time, [3] was chosen because I did not have enough information about the other platforms than UniPhier. That commit also says "The preferred value may vary by platform. If so, please trade up to a different solution." My intention was to replace [3] with [2], not keep both [2] and [3]. Now that we have switched to [2] for SOCFPGA's SPARE_AREA_SKIP_BYTES=2, [3] should be removed. This should be OK because denali_pci.c just gets back to the original behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: denali_dt: add reset controllingMasahiro Yamada1-1/+39
According to the Denali NAND Flash Memory Controller User's Guide, this IP has two reset signals. rst_n: reset most of FFs in the controller core reg_rst_n: reset all FFs in the register interface, and in the initialization sequencer This commit supports controlling those reset signals. It is possible to control them separately from the IP point of view although they might be often tied up together in actual SoC integration. The IP spec says, asserting only the reg_rst_n without asserting rst_n will cause unpredictable behavior in the controller. So, the driver deasserts ->rst_reg and ->rst in this order. Another thing that should be kept in mind is the automated initialization sequence (a.k.a. 'bootstrap' process) is kicked off when reg_rst_n is deasserted. When the reset is deasserted, the controller issues a RESET command to the chip select 0, and attempts to read out the chip ID, and further more, ONFI parameters if it is an ONFI-compliant device. Then, the controller sets up the relevant registers based on the detected device parameters. This process might be useful for tiny boot firmware, but is redundant for Linux Kernel because nand_scan_ident() probes devices and sets up parameters accordingly. Rather, this hardware feature is annoying because it ends up with misdetection due to bugs. So, commit 0615e7ad5d52 ("mtd: nand: denali: remove Toshiba and Hynix specific fixup code") changed the driver to not rely on it. However, there is no way to prevent it from running. The IP provides the 'bootstrap_inhibit_init' port to suppress this sequence, but it is usually out of software control, and dependent on SoC implementation. As for the Socionext UniPhier platform, LD4 always enables it. For the later SoCs, the bootstrap sequence runs depending on the boot mode. I added usleep_range() to make the driver wait until the sequence finishes. Otherwise, the driver would fail to detect the chip due to the race between the driver and hardware-controlled sequence. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: denali_dt: Add support for configuring SPARE_AREA_SKIP_BYTESMarek Vasut2-3/+15
The SPARE_AREA_SKIP_BYTES register is reset when the controller reset signal is toggled. Yet, this register must be configured to match the content of the NAND OOB area. The current default value is always set to 8 and is programmed into the hardware in case the hardware was not programmed before (e.g. in a bootloader) with a different value. This however does not work when the block is reset properly by Linux. On Altera SoCFPGA CycloneV, ArriaV and Arria10, which are the SoCFPGA platforms which support booting from NAND, the SPARE_AREA_SKIP_BYTES value must be set to 2. On Socionext Uniphier, the value is 8. This patch adds support for preconfiguring the default value and handles the special SoCFPGA case by setting the default to 2 on all SoCFPGA platforms, while retaining the original behavior and default value of 8 on all the other platforms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> To: linux-mtd@lists.infradead.org Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: denali_dt: error out if platform has no associated dataMasahiro Yamada1-5/+6
denali->ecc_caps is a mandatory parameter. If it were left unset, nand_ecc_choose_conf() would end up with NULL pointer access. So, every compatible must be associated with proper denali_dt_data. If of_device_get_match_data() returns NULL, let it fail immediately. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: brcmnand: Set appropriate DMA maskFlorian Fainelli1-0/+10
NAND controllers >= 7.0 with FLASH_DMA support physical addresses up to 40-bit, set an appropriate DMA mask for that purpose. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-21mtd: rawnand: mpc5121: Remove unneeded semicolonzhengbin1-1/+1
Fixes coccicheck warning: drivers/mtd/nand/raw/mpc5121_nfc.c:441:2-3: Unneeded semicolon Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-18mtd: rawnand: gpmi: Restore nfc timing setup after suspend/resumeEsben Haabendal1-0/+4
As we reset the GPMI block at resume, the timing parameters setup by a previous exec_op is lost. Rewriting GPMI timing registers on first exec_op after resume fixes the problem. Fixes: ef347c0cfd61 ("mtd: rawnand: gpmi: Implement exec_op") Cc: stable@vger.kernel.org Signed-off-by: Esben Haabendal <esben@geanix.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-18mtd: rawnand: gpmi: Fix suspend/resume problemEsben Haabendal1-1/+6
On system resume, the gpmi clock must be enabled before accessing gpmi block. Without this, resume causes something like [ 661.348790] gpmi_reset_block(5cbb0f7e): module reset timeout [ 661.348889] gpmi-nand 1806000.gpmi-nand: Error setting GPMI : -110 [ 661.348928] PM: dpm_run_callback(): platform_pm_resume+0x0/0x44 returns -110 [ 661.348961] PM: Device 1806000.gpmi-nand failed to resume: error -110 Fixes: ef347c0cfd61 ("mtd: rawnand: gpmi: Implement exec_op") Cc: stable@vger.kernel.org Signed-off-by: Esben Haabendal <esben@geanix.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-09mtd: cadence: Fix cast to pointer from integer of different size warningVasyl Gomonovych1-7/+6
Use dma_addr_t type to pass memory address and control data in DMA descriptor fields memory_pointer and ctrl_data_ptr To fix warning: cast to pointer from integer of different size Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-09mtd: rawnand: stm32_fmc2: avoid to lock the CPU busChristophe Kerello1-2/+36
We are currently using nand_soft_waitrdy to poll the status of the NAND flash. FMC2 enables the wait feature bit (this feature is mandatory for the sequencer mode). By enabling this feature, we can't poll the status of the NAND flash, the read status command is stucked in FMC2 pipeline until R/B# signal is high, and locks the CPU bus. To avoid to lock the CPU bus, we poll FMC2 ISR register. This register reports the status of the R/B# signal. Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig3-5/+5
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2019-11-17Merge tag 'nand/for-5.5' into mtd/nextMiquel Raynal8-60/+3072
Raw NAND core * Useless extra checks dropped. * Updated the detection of the bad block markers position Raw NAND controller drivers: * Cadence : New driver * Brcmnand: Support for flash-dma v0 + fixes * Denali : Support for the legacy controller/chip DT representation dropped * Superfluous dev_err() calls removed
2019-11-17Merge tag 'spi-nor/for-5.5' into mtd/nextMiquel Raynal1-3/+2
SPI NOR core changes: - introduce 'struct spi_nor_controller_ops', - clean the Register Operations methods, - use dev_dbg insted of dev_err for low level info, - fix retlen handling in sst_write(), - fix silent truncations in spi_nor_read and spi_nor_read_raw(), - fix the clearing of QE bit on lock()/unlock(), - rework the disabling of the block write protection, - rework the Quad Enable methods, - make sure nor->spimem and nor->controller_ops are mutually exclusive, - set default Quad Enable method for ISSI flashes, - add support for few flashes. SPI NOR controller drivers changes: - intel-spi: - support chips without software sequencer, - add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
2019-10-30mtd: rawnand: remove unecessary checking if dmac is NULLPiotr Sroka1-2/+2
Remove unecessary checking if dmac is NULL. If Cadence nand controller driver uses DMA engine then cdns_ctrl->dmac cannot be NULL. It is verified during driver initialization. If Cadence nand controller driver does not use DMA engine then CPU IO read/write are executed instead of slave DMA transfer. In that case cdns_ctrl->dmac is not used at all. Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Piotr Sroka <piotrs@cadence.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: cadence: Remove dev_err() on platform_get_irq() failureYueHaibing1-3/+2
platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: mxic: Remove dev_err() on platform_get_irq() failureYueHaibing1-3/+1
platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: brcmnand: Fix NULL pointer assignmentFlorian Fainelli1-1/+1
Sparse complained about the following: drivers/mtd/nand/raw/brcmnand/brcmnand.c:921:40: warning: Using plain integer as NULL pointer fix this issue by assigning the pointer to NULL. Fixes: c1ac2dc34b51 ("mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: denali: remove the old unified controller/chip DT supportMasahiro Yamada1-51/+4
Commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips") supported the new binding for the separate controller/chip representation, keeping the backward compatibility. All the device trees in upstream migrated to the new binding. Remove the support for the old binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-08mtd: Remove dev_err() usage after platform_get_irq()Stephen Boyd11-33/+10
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-07mtd: rawnand: au1550nd: Fix au_read_buf16() prototypePaul Burton1-3/+2
Commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") modified the prototype of the struct nand_chip read_buf function pointer. In the au1550nd driver we have 2 implementations of read_buf. The previously mentioned commit modified the au_read_buf() implementation to match the function pointer, but not au_read_buf16(). This results in a compiler warning for MIPS db1xxx_defconfig builds: drivers/mtd/nand/raw/au1550nd.c:443:57: warning: pointer type mismatch in conditional expression Fix this by updating the prototype of au_read_buf16() to take a struct nand_chip pointer as its first argument, as is expected after commit 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks"). Note that this shouldn't have caused any functional issues at runtime, since the offset of the struct mtd_info within struct nand_chip is 0 making mtd_to_nand() effectively a type-cast. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 7e534323c416 ("mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks") Cc: stable@vger.kernel.org # v4.20+ Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-04mtd: rawnand: Add new Cadence NAND driver to MTD subsystemPiotr Sroka3-0/+3039
Add new Cadence NAND driver to MTD subsystem Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-04mtd: rawnand: Change calculating of position page containing BBMPiotr Sroka2-3/+9
Change calculating of position page containing BBM If none of BBM flags are set then function nand_bbm_get_next_page reports EINVAL. It causes that BBM is not read at all during scanning factory bad blocks. The result is that the BBT table is build without checking factory BBM at all. For Micron flash memories none of these flags are set if page size is different than 2048 bytes. Address this regression by: - adding NAND_BBM_FIRSTPAGE chip flag without any condition. It solves issue only for Micron devices. - changing the nand_bbm_get_next_page_function. It will return 0 if no of BBM flag is set and page parameter is 0. After that modification way of discovering factory bad blocks will work similar as in kernel version 5.1. Cc: stable@vger.kernel.org Fixes: f90da7818b14 (mtd: rawnand: Support bad block markers in first, second or last page) Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-04mtd: nand: brcmnand: Add support for flash-dma v0Kamal Dasu1-2/+19
This change adds support for flash dma v0.0. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-09-22Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds3-544/+0
Pull MIPS updates from Paul Burton: "Main MIPS changes: - boot_mem_map is removed, providing a nice cleanup made possible by the recent removal of bootmem. - Some fixes to atomics, in general providing compiler barriers for smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs or MIPS32 systems using cmpxchg64(). - Conversion to the new generic VDSO infrastructure courtesy of Vincenzo Frascino. - Removal of undefined behavior in set_io_port_base(), fixing the behavior of some MIPS kernel configurations when built with recent clang versions. - Initial MIPS32 huge page support, functional on at least Ingenic SoCs. - pte_special() is now supported for some configurations, allowing among other things generic fast GUP to be used. - Miscellaneous fixes & cleanups. And platform specific changes: - Major improvements to Ingenic SoC support from Paul Cercueil, mostly enabled by the inclusion of the new TCU (timer-counter unit) drivers he's spent a very patient year or so working on. Plus some fixes for X1000 SoCs from Zhou Yanjie. - Netgear R6200 v1 systems are now supported by the bcm47xx platform. - DT updates for BMIPS, Lantiq & Microsemi Ocelot systems" * tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits) MIPS: Detect bad _PFN_SHIFT values MIPS: Disable pte_special() for MIPS32 with RiXi MIPS: ralink: deactivate PCI support for SOC_MT7621 mips: compat: vdso: Use legacy syscalls as fallback MIPS: Drop Loongson _CACHE_* definitions MIPS: tlbex: Remove cpu_has_local_ebase MIPS: tlbex: Simplify r3k check MIPS: Select R3k-style TLB in Kconfig MIPS: PCI: refactor ioc3 special handling mips: remove ioremap_cachable mips/atomic: Fix smp_mb__{before,after}_atomic() mips/atomic: Fix loongson_llsc_mb() wreckage mips/atomic: Fix cmpxchg64 barriers MIPS: Octeon: remove duplicated include from dma-octeon.c firmware: bcm47xx_nvram: Allow COMPILE_TEST firmware: bcm47xx_nvram: Correct size_t printf format MIPS: Treat Loongson Extensions as ASEs MIPS: Remove dev_err() usage after platform_get_irq() MIPS: dts: mscc: describe the PTP ready interrupt MIPS: dts: mscc: describe the PTP register range ...
2019-09-16Merge tag 'nand/for-5.4' of ↵Richard Weinberger15-389/+642
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/for-5.4 NAND core * Fixing typos * Adding missing of_node_put() in various drivers Raw NAND controller drivers: * Macronix: new controller driver * Omap2: Fixing the number of bitflips returned * Brcmnand: Fix a pointer not iterating over all the page chunks * W90x900: Driver removed * Onenand: Fix a memory leak * Sharpsl: Missing include guard * STM32: Avoid warnings when building with W=1 * Ingenic: Fix a coccinelle warning * r852: Call a helper to simplify the code
2019-08-29mtd: rawnand: omap2: Fix number of bitflips reporting with ELMSascha Hauer1-1/+1
omap_elm_correct_data() returns the number of bitflips for the whole page. This is wrong, it should return the maximum number of bitflips found in each ECC step. In my case with a 4k page size NAND mtcdore reported -EUCLEAN with only 12 bitflips on a page where we could correct up to 128 bits per page (provided they are distributed equally on the 8 ECC steps) Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-16 00:22:14 +0300