summaryrefslogtreecommitdiff
path: root/drivers/mmc
AgeCommit message (Expand)AuthorFilesLines
2018-10-08mmc: meson-mx-sdio: mark expected switch fall-throughGustavo A. R. Silva1-1/+1
2018-10-08mmc: tifm_sd: Mark expected switch fall-throughGustavo A. R. Silva1-1/+2
2018-10-08mmc: mmci: Change struct members from bool to u8Ludovic Barre1-16/+16
2018-10-08mmc: mmci: internalize dma_inprogress into mmci dma functionsLudovic Barre2-8/+10
2018-10-08mmc: mmci: internalize dma map/unmap into mmci dma functionsLudovic Barre1-23/+17
2018-10-08mmc: sdhci-pci-o2micro: Add quirk for O2 Micro dev 0x8620 rev 0x01Yu Zhao1-0/+3
2018-10-08mmc: omap_hsmmc: Delete platform data GPIO CD and WPLinus Walleij1-51/+1
2018-10-08mmc: omap_hsmmc: Kill off cover detectionLinus Walleij1-119/+2
2018-10-08mmc: core: Allow building PWRSEQ_SD8787 with LIBERTAS_SDIOLubomir Rintel1-1/+1
2018-10-08mmc: sdhci: sirf: Use the slot GPIO descriptorLinus Walleij1-23/+5
2018-10-08mmc: sdhci: pxav3: Delete GPIO handlingLinus Walleij1-14/+0
2018-10-08mmc: sdhci: spear: Use the slot GPIO descriptorLinus Walleij1-28/+5
2018-10-08mmc: mmci: Drop support for pdata GPIO numbersLinus Walleij1-28/+6
2018-10-08mmc: sdhci: fix __sdhci_adma_write_descJisheng Zhang1-2/+2
2018-10-08mmc: mxcmmc: replace spin_lock_irqsave with spin_lock in ISRjun qian1-3/+2
2018-10-08mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment sizeNiklas Söderlund1-0/+8
2018-10-08mmc: sunxi: Use new timing mode for A64 eMMC controllerChen-Yu Tsai1-0/+1
2018-10-08mmc: sunxi: Clarify new timing mode usage and implementationChen-Yu Tsai1-6/+17
2018-10-08mmc: sdhci-sprd: Add Spreadtrum's initial host controllerChunyan Zhang3-0/+512
2018-10-08mmc: sdhci: SDMA may use Auto-CMD23 in v4 modeChunyan Zhang1-2/+5
2018-10-08mmc: sdhci: Add Auto CMD Auto Select supportChunyan Zhang2-10/+41
2018-10-08mmc: sdhci: Add 32-bit block count support for v4 modeChunyan Zhang2-1/+21
2018-10-08mmc: sdhci: Add ADMA2 64-bit addressing support for V4 modeChunyan Zhang2-26/+78
2018-10-08mmc: sdhci: Change SDMA address register for v4 modeChunyan Zhang1-10/+20
2018-10-08mmc: sdhci: Add sd host v4 modeChunyan Zhang2-0/+32
2018-10-08mmc: sdhci: Add version V4 definitionChunyan Zhang2-1/+4
2018-10-08mmc: tegra: fix inconsistent IS_ERR and PTR_ERRYueHaibing1-1/+1
2018-10-08mmc: tegra: Implement periodic pad calibrationAapo Vienamo1-0/+22
2018-10-08mmc: tegra: Implement HS400 delay line calibrationAapo Vienamo1-0/+29
2018-10-08mmc: tegra: Implement HS400 enhanced strobeAapo Vienamo1-0/+23
2018-10-08mmc: tegra: Parse and program DQS trim valueAapo Vienamo1-3/+29
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra186Aapo Vienamo1-1/+3
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra210Aapo Vienamo1-1/+3
2018-10-08mmc: tegra: Disable card clock during tuning cmd on Tegra210Aapo Vienamo1-23/+58
2018-10-08mmc: tegra: Remove tegra_sdhci_writew() from tegra210_sdhci_opsAapo Vienamo1-1/+0
2018-10-08mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186Aapo Vienamo1-2/+15
2018-10-08mmc: tegra: Configure default trim value on resetAapo Vienamo1-1/+6
2018-10-08mmc: tegra: Configure default tap valuesAapo Vienamo1-55/+77
2018-10-08mmc: tegra: Parse default trim and tap from dtAapo Vienamo1-0/+22
2018-10-08mmc: tegra: Add a workaround for tap value change glitchAapo Vienamo1-2/+28
2018-10-08mmc: tegra: Enable pad calibration on Tegra210 and Tegra186Aapo Vienamo1-2/+4
2018-10-08mmc: tegra: Perform pad calibration after voltage switchAapo Vienamo1-0/+5
2018-10-08mmc: tegra: Program pad autocal offsets from dtAapo Vienamo1-1/+151
2018-10-08mmc: tegra: Disable card clock during pad calibrationAapo Vienamo1-0/+26
2018-10-08mmc: tegra: Power on the calibration padAapo Vienamo1-0/+26
2018-10-08mmc: tegra: Set calibration pad voltage referenceAapo Vienamo1-23/+33
2018-10-08mmc: tegra: Poll for calibration completionAapo Vienamo1-5/+17
2018-10-08mmc: tegra: Reconfigure pad voltages during voltage switchingAapo Vienamo1-7/+129
2018-10-08mmc: tmio: remove now unused variableWolfram Sang1-1/+1
2018-10-08mmc: tmio: more concise clk calculationWolfram Sang1-8/+3
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-07 03:39:50 +0300