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path: root/drivers/mmc/host/sdhci-of-dwcmshc.c
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2024-10-10mmc: sdhci-of-dwcmshc: Prevent stale command interrupt handlingMichal Wilczynski1-0/+8
While working with the T-Head 1520 LicheePi4A SoC, certain conditions arose that allowed me to reproduce a race issue in the sdhci code. To reproduce the bug, you need to enable the sdio1 controller in the device tree file `arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi` as follows: &sdio1 { bus-width = <4>; max-frequency = <100000000>; no-sd; no-mmc; broken-cd; cap-sd-highspeed; post-power-on-delay-ms = <50>; status = "okay"; wakeup-source; keep-power-in-suspend; }; When resetting the SoC using the reset button, the following messages appear in the dmesg log: [ 8.164898] mmc2: Got command interrupt 0x00000001 even though no command operation was in progress. [ 8.174054] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 8.180503] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 [ 8.186950] mmc2: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 8.193395] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 8.199841] mmc2: sdhci: Present: 0x03da0000 | Host ctl: 0x00000000 [ 8.206287] mmc2: sdhci: Power: 0x0000000f | Blk gap: 0x00000000 [ 8.212733] mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x0000decf [ 8.219178] mmc2: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 [ 8.225622] mmc2: sdhci: Int enab: 0x00ff1003 | Sig enab: 0x00ff1003 [ 8.232068] mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 8.238513] mmc2: sdhci: Caps: 0x3f69c881 | Caps_1: 0x08008177 [ 8.244959] mmc2: sdhci: Cmd: 0x00000502 | Max curr: 0x00191919 [ 8.254115] mmc2: sdhci: Resp[0]: 0x00001009 | Resp[1]: 0x00000000 [ 8.260561] mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 [ 8.267005] mmc2: sdhci: Host ctl2: 0x00001000 [ 8.271453] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 [ 8.278594] mmc2: sdhci: ============================================ I also enabled some traces to better understand the problem: kworker/3:1-62 [003] ..... 8.163538: mmc_request_start: mmc2: start struct mmc_request[000000000d30cc0c]: cmd_opcode=5 cmd_arg=0x0 cmd_flags=0x2e1 cmd_retries=0 stop_opcode=0 stop_arg=0x0 stop_flags=0x0 stop_retries=0 sbc_opcode=0 sbc_arg=0x0 sbc_flags=0x0 sbc_retires=0 blocks=0 block_size=0 blk_addr=0 data_flags=0x0 tag=0 can_retune=0 doing_retune=0 retune_now=0 need_retune=0 hold_retune=1 retune_period=0 <idle>-0 [000] d.h2. 8.164816: sdhci_cmd_irq: hw_name=ffe70a0000.mmc quirks=0x2008008 quirks2=0x8 intmask=0x10000 intmask_p=0x18000 irq/24-mmc2-96 [000] ..... 8.164840: sdhci_thread_irq: msg= irq/24-mmc2-96 [000] d.h2. 8.164896: sdhci_cmd_irq: hw_name=ffe70a0000.mmc quirks=0x2008008 quirks2=0x8 intmask=0x1 intmask_p=0x1 irq/24-mmc2-96 [000] ..... 8.285142: mmc_request_done: mmc2: end struct mmc_request[000000000d30cc0c]: cmd_opcode=5 cmd_err=-110 cmd_resp=0x0 0x0 0x0 0x0 cmd_retries=0 stop_opcode=0 stop_err=0 stop_resp=0x0 0x0 0x0 0x0 stop_retries=0 sbc_opcode=0 sbc_err=0 sbc_resp=0x0 0x0 0x0 0x0 sbc_retries=0 bytes_xfered=0 data_err=0 tag=0 can_retune=0 doing_retune=0 retune_now=0 need_retune=0 hold_retune=1 retune_period=0 Here's what happens: the __mmc_start_request function is called with opcode 5. Since the power to the Wi-Fi card, which resides on this SDIO bus, is initially off after the reset, an interrupt SDHCI_INT_TIMEOUT is triggered. Immediately after that, a second interrupt SDHCI_INT_RESPONSE is triggered. Depending on the exact timing, these conditions can trigger the following race problem: 1) The sdhci_cmd_irq top half handles the command as an error. It sets host->cmd to NULL and host->pending_reset to true. 2) The sdhci_thread_irq bottom half is scheduled next and executes faster than the second interrupt handler for SDHCI_INT_RESPONSE. It clears host->pending_reset before the SDHCI_INT_RESPONSE handler runs. 3) The pending interrupt SDHCI_INT_RESPONSE handler gets called, triggering a code path that prints: "mmc2: Got command interrupt 0x00000001 even though no command operation was in progress." To solve this issue, we need to clear pending interrupts when resetting host->pending_reset. This ensures that after sdhci_threaded_irq restores interrupts, there are no pending stale interrupts. The behavior observed here is non-compliant with the SDHCI standard. Place the code in the sdhci-of-dwcmshc driver to account for a hardware-specific quirk instead of the core SDHCI code. Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 43658a542ebf ("mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20241008100327.4108895-1-m.wilczynski@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-28mmc: sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoCLiming Sun1-1/+28
The eMMC RST_N register is implemented as secure register on the BlueField-3 SoC and controlled by TF-A. This commit adds the hw_reset() support which sends an SMC call to TF-A for the eMMC HW reset. Reviewed-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Link: https://lore.kernel.org/r/20240827164016.237617-1-limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: Add support for Sophgo SG2042Chen Wang1-7/+118
Add support for the mmc controller of Sophgo SG2042. SG2042 uses Synopsys PHY the same as TH1520 so we reuse the tuning logic from TH1520. Besides this, this patch implement some SG2042 specific work, such as clocks and reset ops. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/eb21847528a6487af54bb80f1ce94adff289cdb0.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: add dwcmshc_pltfm_dataChen Wang1-33/+48
Abstract dwcmshc_pltfm_data to hold the sdhci_pltfm_data plus some comoon operations of soc such as init/postinit. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/cb2c68c594286e9588c53acb76163e60c140c02b.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: factor out code into dwcmshc_rk35xx_initChen Wang1-18/+16
Continue factor out code fron probe into dwcmshc_rk35xx_init. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/4f1f2fa403ce7f0b4d79afb7d7e8a1690cde5d6c.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: factor out code for th1520_init()Chen Wang1-21/+30
Different socs have initialization operations in the probe process, which are summarized as functions. This patch first factor out init function for th1520. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Drew Fustini <drew@pdp7.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/23c6a81052a6dd3660d60348731229d60a209b32.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: move two rk35xx functionsChen Wang1-45/+45
This patch just move dwcmshc_rk35xx_init() and dwcmshc_rk35xx_postinit() to put the functions of rk35xx together as much as possible. This change is an intermediate process before further modification. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/54204702d5febd3e867eb3544c36919fe4140a88.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: add common bulk optional clocks supportChen Wang1-42/+48
In addition to the required core clock and optional bus clock, the soc will expand its own clocks, so the bulk clock mechanism is abstracted. Note, I call the bulk clocks as "other clocks" due to the bus clock has been called as "optional". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/e57e8c51da81f176b49608269a884f840903e78e.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-06-20mmc: sdhci-of-dwcmshc: set CQE irq-handler for rockchip variantsHeiko Stuebner1-0/+1
The dwcmshc used on Rockchip rk3568 and rk3588 can use cqe, so set the needed irq handler. Tested on a rk3588-tiger SoM with dd, hdparm and fio. fio performance does increase slightly from Run status group 0 (all jobs): READ: bw=209MiB/s (219MB/s), 209MiB/s-209MiB/s (219MB/s-219MB/s), io=4096MiB (4295MB), run=19607-19607msec without CQE to Run status group 0 (all jobs): READ: bw=215MiB/s (225MB/s), 215MiB/s-215MiB/s (225MB/s-225MB/s), io=4096MiB (4295MB), run=19062-19062msec with CQE enabled. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240530215547.2192457-1-heiko@sntech.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-04-26mmc: sdhci-of-dwcmshc: Add tuning support for Sophgo CV1800B and SG200XJisheng Zhang1-0/+112
Implement the .platform_execute_tuning for Sophgo CV1800B and SG200X. Some code is borrowed from sdhci-esdhc-imx.c. The tuning result is similar as the one of SoC vendor's SDK. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240420021429.454-1-jszhang@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-04-26mmc: sdhci-of-dwcmshc: Remove useless "&" of th1520_execute_tuningJisheng Zhang1-1/+1
The preceding "&" before th1520_execute_tuning is useless, remove it. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240414164357.2841-1-jszhang@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-04-04mmc: Merge branch fixes into nextUlf Hansson1-0/+1
Merge the mmc fixes for v6.9-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.10. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-04-04mmc: sdhci-of-dwcmshc: th1520: Increase tuning loop count to 128Maksim Kiselev1-0/+1
Fix SD card tuning error by increasing tuning loop count from 40(MAX_TUNING_LOOP) to 128. For some reason the tuning algorithm requires to move through all the taps of delay line even if the THRESHOLD_MODE (bit 2 in AT_CTRL_R) is used instead of the LARGEST_WIN_MODE. Tested-by: Drew Fustini <drew@pdp7.com> Tested-by: Xi Ruoyao <xry111@xry111.site> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 43658a542ebf ("mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240402093539.184287-1-bigunclemax@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-04-02mmc: sdhci-of-dwcmshc: Implement SDHCI CQE supportSergey Khimich1-2/+189
For enabling CQE support just set 'supports-cqe' in your DevTree file for appropriate mmc node. Signed-off-by: Sergey Khimich <serghox@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240319115932.4108904-3-serghox@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-03-25sdhci-of-dwcmshc: disable PM runtime in dwcmshc_remove()Liming Sun1-11/+17
This commit disables PM runtime in dwcmshc_remove() to avoid the error message below when reloading the sdhci-of-dwcmshc.ko sdhci-dwcmshc MLNXBF30:00: Unbalanced pm_runtime_enable! Fixes: 48fe8fadbe5e ("mmc: sdhci-of-dwcmshc: Add runtime PM operations") Reviewed-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/b9155963ffb12d18375002bf9ac9a3f98b727fc8.1710854108.git.limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-02-27mmc: sdhci-of-dwcmshc: Add support for Sophgo CV1800B and SG2002Jisheng Zhang1-0/+66
Add support for the mmc controller in the Sophgo CV1800B and SG2002 with corresponding new compatible strings. Implement custom sdhci_ops. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Link: https://lore.kernel.org/r/20240217144202.3808-3-jszhang@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07mmc: sdhci-of-dwcmshc: Use logical OR instead of bitwise OR in dwcmshc_probe()Nathan Chancellor1-3/+3
Clang warns (or errors with CONFIG_WERROR=y): drivers/mmc/host/sdhci-of-dwcmshc.c:873:7: error: use of bitwise '|' with boolean operands [-Werror,-Wbitwise-instead-of-logical] 873 | if ((device_property_read_bool(dev, "mmc-ddr-1_8v")) | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 874 | (device_property_read_bool(dev, "mmc-hs200-1_8v")) | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | || 875 | (device_property_read_bool(dev, "mmc-hs400-1_8v"))) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mmc/host/sdhci-of-dwcmshc.c:873:7: note: cast one or both operands to int to silence this warning drivers/mmc/host/sdhci-of-dwcmshc.c:873:7: error: use of bitwise '|' with boolean operands [-Werror,-Wbitwise-instead-of-logical] 873 | if ((device_property_read_bool(dev, "mmc-ddr-1_8v")) | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | || 874 | (device_property_read_bool(dev, "mmc-hs200-1_8v")) | | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mmc/host/sdhci-of-dwcmshc.c:873:7: note: cast one or both operands to int to silence this warning 2 errors generated. There is little reason for this if statement to use bitwise ORs, as the short circuiting of logical OR does not need to be avoided in this context; it would be wasteful to call device_property_read_bool() three times if the first two calls returned true. Switch to logical OR to fix the warning. While in the area, the parentheses around the calls to device_property_read_bool() are not necessary and make the if statement harder to read, so remove them. Closes: https://github.com/ClangBuiltLinux/linux/issues/1960 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20231116-sdhci-of-dwcmshc-fix-wbitwise-instead-of-logical-v1-1-7e1a7f4ccaab@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-12-07mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520Drew Fustini1-0/+349
Add support for the mmc controller in the T-Head TH1520 with the new compatible "thead,th1520-dwcmshc". Implement custom sdhci_ops for set_uhs_signaling, reset, voltage_switch, and platform_execute_tuning. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20231109-th1520-mmc-v5-3-018bd039cf17@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-08-24mmc: sdhci-of-dwcmshc: Add runtime PM operationsLiming Sun1-2/+62
This commit implements the runtime PM operations to disable eMMC card clock when idle. Reviewed-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230822195929.168552-2-limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-08-24mmc: sdhci-of-dwcmshc: Add error handling in dwcmshc_resumeLiming Sun1-3/+18
This commit adds handling in dwcmshc_resume() for different error cases. Signed-off-by: Liming Sun <limings@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230822195929.168552-1-limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-08-15mmc: sdhci-of-dwcmshc: Convert to platform remove callback returning voidYangtao Li1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230727070051.17778-26-frank.li@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-08-09mmc: Explicitly include correct DT includesRob Herring1-1/+1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230718143054.1065288-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-03-23mmc: sdhci-of-dwcmshc: properly determine max clock on RockchipVasily Khoruzhick1-1/+8
Currently .get_max_clock returns the current clock rate for cclk_emmc on rk35xx, thus max clock gets set to whatever bootloader set it to. In case of u-boot, it is intentionally reset to 50 MHz if it boots from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit clears appropriate caps if host->mmc->f_max is < 52MHz cclk_emmc is not a fixed clock on rk35xx, so using sdhci_pltfm_clk_get_max_clock is not appropriate here. Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-02-14mmc: sdhci-of-dwcmshc: add the missing device table IDs for acpiLiming Sun1-0/+1
This commit adds the missing MODULE_DEVICE_TABLE for acpi, or else it won't be loaded automatically when compiled as a kernel module. Reviewed-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Link: https://lore.kernel.org/r/f57ad0f8fdf663465bca74467c344dfa305a3199.1675305696.git.limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-02-14mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for rockchip platformShawn Lin1-4/+9
For Rockchip platform, DLL bypass bit and start bit need to be set if DLL is not locked. And adjust pre-change delay to 0x3 for better signal test result. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-01-23mmc: sdhci-of-dwcmshc: enable host V4 support for BlueField-3 SoCLiming Sun1-0/+5
This commit enables SDHCI Host V4 support on Bluefield-3 SoC to be consistent with the default setting in firmware(UEFI). Reviewed-by: David Woods <davwoods@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/990885f566c32ac8e6888ad6b434fb70d1a5d7af.1673460632.git.limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2022-08-15mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoCLiming Sun1-2/+14
The commit 08f3dff799d4 (mmc: sdhci-of-dwcmshc: add rockchip platform support") introduces the use of_device_get_match_data() to check for some chips. Unfortunately, it also breaks the BlueField-3 FW, which uses ACPI. To fix the problem, let's add the ACPI match data and the corresponding quirks to re-enable the support for the BlueField-3 SoC. Reviewed-by: David Woods <davwoods@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220809173742.178440-1-limings@nvidia.com [Ulf: Clarified the commit message a bit] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2022-07-12mmc: sdhci-of-dwcmshc: add support for rk3588Yifeng Zhao1-18/+103
Add support for RK3588's DWCMSHC controller, which is used for providing the rootfs on the RK3588 evaluation board. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> [port from vendor BSP] Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220504213251.264819-12-sebastian.reichel@collabora.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2022-07-12mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xxSebastian Reichel1-23/+23
Prepare driver for rk3588 support by renaming the internal data structures. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2022-07-12mmc: sdhci-of-dwcmshc: add reset call back for rockchip SocsYifeng Zhao1-1/+25
The reset function build in the SDHCI will not reset the logic circuit related to the tuning function, which may cause data reading errors. Resetting the complete SDHCI controller through the reset controller fixes the issue. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> [rebase, use optional variant of reset getter] Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci-of-dwcmshc: set MMC_CAP_WAIT_WHILE_BUSYJisheng Zhang1-0/+2
The host supports HW busy detection of the device busy signaling over dat0 line. Set MMC_CAP_wAIT_WHILE_BUSY host capability. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20210324154703.69f97fde@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci-of-dwcmshc: fix error return code in dwcmshc_probe()Wei Yongjun1-1/+3
Fix to return negative error code -ENOMEM from the error handling case instead of 0, as done elsewhere in this function. Fixes: c2c4da37837e ("mmc: sdhci-of-dwcmshc: add rockchip platform support") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20210323112956.1016884-1-weiyongjun1@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci-of-dwcmshc: add ACPI support for BlueField-3 SoCLiming Sun1-14/+36
This commit adds ACPI support in the sdhci-of-dwcmshc driver for BlueField-3 SoC. It has changes to only use the clock hierarchy for Deviec Tree since the clk is not supported by ACPI. Instead, ACPI can define 'clock-frequency' which is parsed by existing sdhci_get_property(). This clock value will be returned in function dwcmshc_get_max_clock(). Signed-off-by: Liming Sun <limings@nvidia.com> Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com> Link: https://lore.kernel.org/r/1616453211-275165-1-git-send-email-limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci-of-dwcmshc: add rockchip platform supportShawn Lin1-8/+253
sdhci based synopsys MMC IP is also used on some rockchip platforms, so add a basic support here. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1615879102-45919-3-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKENJisheng Zhang1-0/+1
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so set the quirk. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20201210165510.76b917e5@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-01-11mmc: sdhci-of-dwcmshc: fix rpmb accessJisheng Zhang1-0/+27
Commit a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB") began to use ACMD23 for RPMB if the host supports ACMD23. In RPMB ACM23 case, we need to set bit 31 to CMD23 argument, otherwise RPMB write operation will return general fail. However, no matter V4 is enabled or not, the dwcmshc's ARGUMENT2 register is 32-bit block count register which doesn't support stuff bits of CMD23 argument. So let's handle this specific ACMD23 case. From another side, this patch also prepare for future v4 enabling for dwcmshc, because from the 4.10 spec, the ARGUMENT2 register is redefined as 32bit block count which doesn't support stuff bits of CMD23 argument. Fixes: a44f7cb93732 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20201229161625.38255233@xhacker.debian Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-07mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.19Douglas Anderson1-0/+1
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.19 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200903162412.4.I84eb3e0a738635d524c90d1a688087bc295f7c32@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-28mmc: sdhci-of-dwcmshc: add suspend/resume supportJisheng Zhang1-0/+43
Add dwcmshc specific system-level suspend and resume support. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200515141926.52e088fe@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-28mmc: sdhci-of-dwcmshc: implement specific set_uhs_signalingJisheng Zhang1-1/+30
We need a different set_uhs_signaling implementation for MMC_TIMING_MMC_HS and MMC_TIMING_MMC_HS400. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200513182602.3636a551@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci-of-dwcmshc: solve 128MB DMA boundary limitationJisheng Zhang1-0/+39
When using DMA, if the DMA addr spans 128MB boundary, we have to split the DMA transfer into two so that each one doesn't exceed the boundary. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-of-dwcmshc: add SDHCI OF Synopsys DWC MSHC driverJisheng Zhang1-0/+116
Add a driver for SDHCI OF Synopsys DesignWare Cores Mobile Storage Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 20:22:47 +0300