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2020-05-28Merge branch 'baikal/drivers' into arm/driversArnd Bergmann3-0/+334
[arnd: This is a patch series from Serge Semin to add a few drivers that don't have any other subsystem maintainer tree to go through, so I'm picking them up through the soc tree, full series description from the mailing list below] Baikal-T1 SoC CPU is based on two MIPS Warrior P5600 cores. Their main memory Non-Coherent IO interface is connected to the OCP2AXI bridge, which in turn is then connected to the DW AMBA 3 AXI Interconnect (so called Main Interconnect) with nine masters and four slaves ports. Main Interconnect is responsible for the AXI-bus traffic arbitration (QoS) and its routing from one component to another. In addition there is a Errors Handler Block (EHB) accesible by means of the Baikal-T1 SoC System Controller responsible to detect AXI protocol errors and device not responding situations built on top the interconnect. Baikal-T1 AXI-bus driver included in this patchset will be responsible for working with that functionality, though currently it doesn't support QoS tuning. Instead it's capable of detecting the error events, reporting an info about them to the system log, injecting artificial errors to test the driver functionality. Since AXI Interconnect doesn't provide a way to find out which devices are connected to it, so its DT node is supposed to be compatible with "simple-bus" driver, while sub-nodes shall represent the masters attached to the bus. One of the AXI Interconnect slaves is an AXI-APB bridge used to access the Baikal-T1 SoC subsystems CSRs. MMIO request from CPU and DMAC masters are routed there if they are detected to be within [0x08000000 0x1FFFFFFF] range of the physical memory. In case if an attempted APB transaction stays with no response for a pre-defined time it will be detected by the APB-bus Errors Handler Block (EHB), which will raise an interrupt, then the bus gets freed for a next operation. The APB-bus driver provides the interrupt handler to detect the erroneous address, update an errors counter and prints an error message about the faulty address. The counter and the APB-bus operations timeout can be accessed via corresponding sysfs nodes. A dedicated sysfs-node can be also used to artificially cause the bus errors described above. Since APB-bus is a platform bus, it doesn't provide a way to detect slave devices connected to it, so similarly to the AXI-bus it's also supposed to be compatible with "simple-bus" driver. Aside from PCIe/SATA/DDR/I2C/EHB/CPU/reboot specific settings the Baikal-T1 System Controller provides a MIPS P5600 CM2 L2-cache tuning block. It is responsible for the setting up the Tag/Data/WS L2-to-RAM latencies. The last small patch in this patchset provides a driver and DT-schema-based binding for the described device. So that the latencies can be tuned up by means of dedicated DT properties and sysfs nodes. This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4. Changelog v2 (AXI/APB bus): - Assign dual GPL/BSD licenses to the bindings. - Use single lined copyright headers in the bindings. - Replace "additionalProperties: false" property with "unevaluatedProperties: false" in the bindings. - Don't use a multi-arg clock phandle reference in DT binding examples. Thus remove includes from there. - Fix some commit message and Kconfig help text spelling. - Move drivers from soc to the bus subsystem. - Convert a simple EHB drivers to the Baikal-T1 AXI and APB bus ones. - Convert APB bus driver to using regmap MMIO API. - Use syscon regmap to access the AXI-bus erroneous address. - Add reset line support. - Add Main Interconnect clock support to the AXI-bus driver. - Remove probe-status info string printout. - Discard of_match_ptr() macro utilization. - Don't print error-message if no platform IRQ found. Just return an error. - Use generic FIELD_{GET,PREP} macros instead of handwritten ones in the AXI-bus driver. Changelog v2 (l2 driver): - Fix some commit message and Kconfig help text spelling. - Move the driver to the memory subsystem. - Assign dual GPL/BSD license to the DT binding. - Use single lined copyright header in the binding. - Discard reg property and syscon compatible string. - Move "allOf" restrictions to the root level of the properties. - The DT node is supposed to be a child of the Baikal-T1 system controller node. So regmap will be fetched from there. - Use generic FIELD_{GET,PREP} macro. - Remove probe-status info string printout. - Since the driver depends on the OF config we can remove of_match_ptr() macro utilization. Changelog v3: - Combine l2 and AXI/APB bus patches in a single patchset. - Retrieve AXI-bus QoS registers by resource name "qos". - Discard CONFIG_OF dependency since there is none at compile-time. - Add syscon EHB registers range to the AXI-bus reg property as optional entry. - Fix invalid of_property_read_u32() return value test in the l2-ctl driver. - Get the reg property back into the l2-ctl DT bindings even though the driver is using the parental syscon regmap. - The l2-ctl DT schema will live separately from the system controller, but the corresponding sub-node of the later DT schema will $ref this one. - Set non-default latencies in the l2-ctl DT example. * baikal/drivers: memory: Add Baikal-T1 L2-cache Control Block driver bus: Add Baikal-T1 APB-bus driver bus: Add Baikal-T1 AXI-bus driver dt-bindings: bus: Add Baikal-T1 APB-bus binding dt-bindings: bus: Add Baikal-T1 AXI-bus binding Link: https://lore.kernel.org/lkml/20200526130841.ap6qlxv7hqmabnh5@mobilestation/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-28memory: Add Baikal-T1 L2-cache Control Block driverSerge Semin3-0/+334
Baikal-T1 SoC provides a way to tune the MIPS P5600 CM2 L2-cache performance up. It can be done by changing the L2-RAM Data/Tag/WS latencies in a dedicated register exposed by the system controller. The driver added by this commit provides a dts properties-based and sysfs-based interface for it. The device DT node is supposed to be a child of Baikal-T1 System Controller node. Link: https://lore.kernel.org/r/20200526125928.17096-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-12memory: samsung: exynos5422-dmc: Reduce protected code area in IRQ handlerBernard Zhao1-4/+2
Speed-up a bit this IRQ processing as there is no need to protect return value or printing. Signed-off-by: Bernard Zhao <bernard@vivo.com> Acked-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-05-08memory: samsung: exynos5422-dmc: Fix tFAW timings alignmentBernard Zhao1-1/+1
Aligning of tFAW timing with standard was using wrong argument as minimum acceptable value. This could lead to wrong timing if provided timings and clock period do not match the standard. Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Cc: <stable@vger.kernel.org> Signed-off-by: Bernard Zhao <bernard@vivo.com> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-04-04Merge tag 'arm-drivers-5.7' of ↵Linus Torvalds3-0/+15
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "These are the usual updates for SoC specific device drivers and related subsystems that don't have their own top-level maintainers: - ARM SCMI/SCPI updates to allow pluggable transport layers - TEE subsystem cleanups - A new driver for the Amlogic secure power domain controller - Various driver updates for the NXP Layerscape DPAA2, NXP i.MX SCU and TI OMAP2+ sysc drivers. - Qualcomm SoC driver updates, including a new library module for "protection domain" notifications - Lots of smaller bugfixes and cleanups in other drivers" * tag 'arm-drivers-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (70 commits) soc: fsl: qe: fix sparse warnings for ucc_slow.c soc: fsl: qe: ucc_slow: remove 0 assignment for kzalloc'ed structure soc: fsl: qe: fix sparse warnings for ucc_fast.c soc: fsl: qe: fix sparse warnings for qe_ic.c soc: fsl: qe: fix sparse warnings for ucc.c soc: fsl: qe: fix sparse warning for qe_common.c soc: fsl: qe: fix sparse warnings for qe.c soc: qcom: Fix QCOM_APR dependencies soc: qcom: pdr: Avoid uninitialized use of found in pdr_indication_cb soc: imx: drop COMPILE_TEST for IMX_SCU_SOC firmware: imx: add COMPILE_TEST for IMX_SCU driver soc: imx: gpc: fix power up sequencing soc: imx: increase build coverage for imx8m soc driver soc: qcom: apr: Add avs/audio tracking functionality dt-bindings: soc: qcom: apr: Add protection domain bindings soc: qcom: Introduce Protection Domain Restart helpers devicetree: bindings: firmware: add ipq806x to qcom_scm memory: tegra: Correct debugfs clk rate-range on Tegra124 memory: tegra: Correct debugfs clk rate-range on Tegra30 memory: tegra: Correct debugfs clk rate-range on Tegra20 ...
2020-03-25.gitignore: add SPDX License IdentifierMasahiro Yamada1-0/+1
Add SPDX License Identifier to all .gitignore files. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-11memory: tegra: Correct debugfs clk rate-range on Tegra124Dmitry Osipenko1-0/+5
Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 6b9acd935546 ("memory: tegra: Refashion EMC debugfs interface on Tegra124") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11memory: tegra: Correct debugfs clk rate-range on Tegra30Dmitry Osipenko1-0/+5
Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11memory: tegra: Correct debugfs clk rate-range on Tegra20Dmitry Osipenko1-0/+5
Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-16Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson1-3/+1
arm/drivers mvebu drivers for 5.6 (part 1) - Various cleanup on the following drivers: - Turris Mox rWTM firmware - Moxtet bus - Armada 37xx rWTM mailbox - Marvell EBU Device Bus * tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu: mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource memory: mvebu-devbus: convert to devm_platform_ioremap_resource bus: moxtet: declare moxtet_bus_type as static firmware: turris-mox-rwtm: small white space cleanup Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'tegra-for-5.6-memory' of ↵Olof Johansson7-149/+1928
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.6-rc1 This adds a couple of fixes for the Tegra30 EMC frequency scaling code and adds support for EMC frequency scaling on Tegra186 and later. * tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence memory: tegra: Correct reset value of xusb_hostr memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later memory: tegra: Add system sleep support memory: tegra: Extract memory client SID programming memory: tegra: Add per-SoC data for Tegra186 memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 memory: tegra: Implement EMC debugfs interface on Tegra30 memory: tegra: Implement EMC debugfs interface on Tegra20 memory: tegra: Refashion EMC debugfs interface on Tegra124 Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10memory: tegra30-emc: Correct error message for timed out auto calibrationDmitry Osipenko1-2/+1
The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra30-emc: Firm up hardware programming sequenceDmitry Osipenko1-61/+89
Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra30-emc: Firm up suspend/resume sequenceDmitry Osipenko1-18/+20
The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10memory: tegra: Correct reset value of xusb_hostrNicolin Chen1-1/+1
According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Add support for the Tegra194 memory controllerThierry Reding3-0/+953
The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Only include support for enabled SoCsThierry Reding2-0/+8
The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Support DVFS on Tegra186 and laterThierry Reding3-3/+304
Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Add system sleep supportThierry Reding1-0/+19
Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Extract memory client SID programmingThierry Reding1-22/+27
Move programming of the memory client to SID mapping into a separate function so that it can be reused from multiple call sites. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Add per-SoC data for Tegra186Thierry Reding1-10/+19
Instead of hard-coding the memory client table, use per-SoC data in preparation for adding support for other SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186Thierry Reding1-4/+10
This is just for consistency with the rest of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra30Thierry Reding1-0/+173
A common debugfs interface is already available on Tegra20, Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra20Thierry Reding1-0/+175
A common debugfs interface is already available on Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra20 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Refashion EMC debugfs interface on Tegra124Thierry Reding1-42/+143
The current debugfs interface is only partially useful. While it allows listing supported frequencies and testing individual clock rates, it is limited in that it can't be used to restrict the range of frequencies that the driver is allowed to set. This is something we may want to use to test adaptive scaling once that's implemented. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08memory: mvebu-devbus: convert to devm_platform_ioremap_resourceYangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-07memory: samsung: Rename Exynos to lowercaseKrzysztof Kozlowski2-2/+2
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-30memory: samsung: exynos5422-dmc: Convert to devm_platform_ioremap_resourceYangtao Li1-5/+2
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-06Merge tag 'tegra-for-5.5-memory-fixes' of ↵Olof Johansson1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes memory: tegra: Fixes for v5.5-rc1 This contains a fix for a kernel panic that can occur on suspend if EMC timings are not available in device tree. * tag 'tegra-for-5.5-memory-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Fix panic on suspend Link: https://lore.kernel.org/r/20191204130753.3614278-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-12-05Merge tag 'armsoc-drivers' of ↵Linus Torvalds18-222/+3327
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...
2019-11-18memory: tegra30-emc: Fix panic on suspendDmitry Osipenko1-1/+1
Trying to suspend driver results in a crash if timings aren't available in device-tree. Reported-by: Jon Hunter <jonathanh@nvidia.com> Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-12Merge tag 'tegra-for-5.5-memory-v2' of ↵Olof Johansson9-149/+1428
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.5-rc1 This contains a couple of fixes and adds support for EMC frequency scaling on Tegra30. * tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits clk: tegra: Add Tegra20/30 EMC clock implementation Link: https://lore.kernel.org/r/20191111143836.4027200-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-11memory: tegra: Consolidate registers definition into common headerDmitry Osipenko4-74/+47
The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Ensure timing control debug features are disabledDmitry Osipenko2-0/+5
Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Introduce Tegra30 EMC driverDmitry Osipenko6-14/+1310
Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Do not handle error from wait_for_completion_timeout()Dmitry Osipenko1-5/+1
Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Increase handshake timeout on Tegra20Dmitry Osipenko1-1/+1
Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Print a brief info message about EMC timingsDmitry Osipenko1-0/+7
During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Pre-configure debug register on Tegra20Dmitry Osipenko1-1/+16
The driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Include io.h instead of iopoll.hDmitry Osipenko1-1/+1
The register polling code was gone, but the included header change was missed. Fix it up for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Adapt for Tegra20 clock driver changesDmitry Osipenko1-2/+48
Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra clock driver API. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Don't set EMC rate to maximum on probe for Tegra20Dmitry Osipenko1-77/+1
The memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Add gr2d and gr3d to DRM IOMMU groupThierry Reding3-12/+19
All of the devices making up the Tegra DRM device want to share a single IOMMU domain. Put them into a single group to allow them to do that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Set DMA mask based on supported address bitsThierry Reding1-0/+10
The memory controller on Tegra124 and later supports 34 or more address bits. Advertise that by setting the DMA mask based on the number of the address bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-08Merge tag 'at91-5.5-drivers' of ↵Olof Johansson1-6/+5
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 drivers for 5.5 - a new driver exposing the serial number registers through nvmem - a few documentation and definition changes * tag 'at91-5.5-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver ARM: at91: Documentation: update the sama5d3 and armv7m datasheets Link: https://lore.kernel.org/r/20191107221644.GA201884@piout.net Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-08memory: atmel-ebi: switch to SPDX license identifiersTudor Ambarus1-4/+1
Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20190906151519.19442-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-11-08memory: atmel-ebi: move NUM_CS definition inside EBI driverTudor Ambarus1-2/+4
The total number of EBI CS lines is described by the EBI controller and not by the Matrix. Move the definition for the number of CS inside EBI driver. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20190906150632.19039-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-11-04Merge branch 'for_5.5/driver-soc' of ↵Olof Johansson1-4/+1
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers * 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs' soc: ti: omap-prm: fix return value check in omap_prm_probe() soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/1572372856-20598-1-git-send-email-santosh.shilimkar@oracle.com Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-29memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'YueHaibing1-4/+1
drivers/memory/emif.c:1616:9: warning: variable cs1_used set but not used [-Wunused-but-set-variable] drivers/memory/emif.c:1624:36: warning: variable custom_configs set but not used [-Wunused-but-set-variable] They are never used since introduction. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2019-10-24Merge tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux ↵Olof Johansson1-63/+101
into arm/drivers This pull request contains Broadcom ARM/ARM64/MIPS based SoCs drivers updates for 5.5, please pull the following: - Markus updates the DPFE driver so as to support deferring the firmware loading process until the first sysfs attribute is accessed, in the process he does a bunch of cleanups and minor fixes - Florian adds support for the DPFE on 7211 which uses a "new style" API v2 and makes necessary changes along the way * tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux: memory: brcmstb: dpfe: Fixup API version/commands for 7211 memory: brcmstb: dpfe: Compute checksum at __send_command() time memory: brcmstb: dpfe: support for deferred firmware download memory: brcmstb: dpfe: pass *priv as argument to brcmstb_dpfe_download_firmware() memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware() memory: brcmstb: dpfe: add locking around DCPU enable/disable memory: brcmstb: dpfe: initialize priv->dev memory: brcmstb: dpfe: rename struct private_data Link: https://lore.kernel.org/r/20191023212814.30622-2-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 07:04:38 +0300