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path: root/drivers/memory/tegra/tegra20-emc.c
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2021-06-10memory: tegra: Delete dead debugfs checking codeDan Carpenter1-4/+0
The debugfs_create_dir() function does not return NULL, it returns error pointers. But in normal situations like this where the caller is not dereferencing "emc->debugfs.root" then we are not supposed to check the return. So instead of fixing these checks, we should delete them. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YMCQDTSyG8UuQoh0@mwanda Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()Dmitry Osipenko1-44/+4
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization. Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-04-01memory: tegra: Print out info-level once per driver probeDmitry Osipenko1-10/+10
Probing of EMC drivers may be deferred and in this case we get duplicated info messages during kernel boot. Use dev_info_once() helper to silence the duplicated messages. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20210330230445.26619-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-01-29memory: tegra: Remove calls to dev_pm_opp_set_clkname()Viresh Kumar1-11/+2
There is no point calling dev_pm_opp_set_clkname() with the "name" parameter set to NULL, this is already done by the OPP core at setup time and should work as it is. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/0f22cc1791d8b88c50a9790c2dc19455b34ec7b0.1611742564.git.viresh.kumar@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-05memory: tegra20: Support hardware versioning and clean up OPP table ↵Dmitry Osipenko1-28/+20
initialization Support hardware versioning, which is now required for Tegra20 EMC OPP. Clean up OPP table initialization by using a error code returned by OPP API for judging about the OPP table presence in a device-tree and remove OPP regulator initialization because we're now going to use power domain instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par with the Tegra30/124 EMC drivers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201203192439.16177-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Add devfreq supportDmitry Osipenko1-0/+90
Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Remove IRQ number from error messageDmitry Osipenko1-1/+1
Remove IRQ number from error message since it doesn't add any useful information, especially because this number is virtual. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201111011456.7875-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Factor out clk initializationDmitry Osipenko1-23/+47
Factor out clk initialization and make it resource-managed. This makes easier to follow code and will help to make further changes cleaner. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201111011456.7875-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Use dev_pm_opp_set_clkname()Dmitry Osipenko1-11/+19
The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use dev_pm_opp_set_clkname() instead. Suggested-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201111011456.7875-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20: Support interconnect frameworkDmitry Osipenko1-3/+307
Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-36-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Continue probing if timings are missing in device-treeDmitry Osipenko1-18/+16
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-35-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra20-emc: Make driver modularDmitry Osipenko1-5/+12
Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201104164923.21238-34-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra: Remove superfluous error messages around platform_get_irq()Dmitry Osipenko1-1/+0
The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-31-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-26memory: tegra: Use devm_platform_ioremap_resource()Dmitry Osipenko1-3/+1
Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201104164923.21238-30-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-06-22memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko1-17/+11
The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-22memory: tegra: Make debugfs permissions human-readableDmitry Osipenko1-3/+3
Replace the symbolic permissions with octals in order to make them readable. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11memory: tegra: Correct debugfs clk rate-range on Tegra20Dmitry Osipenko1-0/+5
Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09memory: tegra: Implement EMC debugfs interface on Tegra20Thierry Reding1-0/+175
A common debugfs interface is already available on Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra20 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Do not handle error from wait_for_completion_timeout()Dmitry Osipenko1-5/+1
Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Increase handshake timeout on Tegra20Dmitry Osipenko1-1/+1
Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Print a brief info message about EMC timingsDmitry Osipenko1-0/+7
During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Pre-configure debug register on Tegra20Dmitry Osipenko1-1/+16
The driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Include io.h instead of iopoll.hDmitry Osipenko1-1/+1
The register polling code was gone, but the included header change was missed. Fix it up for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Adapt for Tegra20 clock driver changesDmitry Osipenko1-2/+48
Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra clock driver API. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11memory: tegra: Don't set EMC rate to maximum on probe for Tegra20Dmitry Osipenko1-77/+1
The memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-08memory: tegra: Introduce Tegra20 EMC driverDmitry Osipenko1-0/+591
Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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