index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
pinetabv-6.6.y-devel
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
media
/
i2c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-12-07
media: ccs: Add support for obtaining C-PHY configuration from firmware
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs-pll: Print pixel rates
Sakari Ailus
1
-0
/
+5
2020-12-07
media: ccs: Print written register values
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs: Add support for DDR OP SYS and OP PIX clocks
Sakari Ailus
1
-1
/
+8
2020-12-07
media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
2
-20
/
+46
2020-12-07
media: ccs: Dual PLL support
Sakari Ailus
2
-3
/
+51
2020-12-07
media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
2
-22
/
+196
2020-12-07
media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
1
-27
/
+37
2020-12-07
media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
1
-5
/
+7
2020-12-07
media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
1
-26
/
+25
2020-12-07
media: ccs-pll: Rework bounds checks
Sakari Ailus
2
-57
/
+95
2020-12-07
media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
1
-19
/
+66
2020-12-07
media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
1
-23
/
+31
2020-12-07
media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
3
-29
/
+64
2020-12-07
media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
1
-124
/
+131
2020-12-07
media: ccs-pll: Add C-PHY support
Sakari Ailus
1
-9
/
+26
2020-12-07
media: ccs-pll: Add sanity checks
Sakari Ailus
1
-0
/
+9
2020-12-07
media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
3
-8
/
+23
2020-12-07
media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
3
-6
/
+16
2020-12-07
media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
3
-1
/
+7
2020-12-07
media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
4
-19
/
+23
2020-12-07
media: ccs: Add support for lane speed model
Sakari Ailus
1
-1
/
+10
2020-12-07
media: ccs-pll: Add support for lane speed model
Sakari Ailus
2
-11
/
+31
2020-12-07
media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
1
-2
/
+1
2020-12-07
media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
1
-2
/
+9
2020-12-07
media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
1
-8
/
+4
2020-12-07
media: ccs-pll: Use the BIT macro
Sakari Ailus
1
-2
/
+5
2020-12-07
media: ccs-pll: Document the structs in the header as well as the function
Sakari Ailus
1
-0
/
+89
2020-12-07
media: ccs-pll: Move the flags field down, away from 8-bit fields
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
3
-3
/
+4
2020-12-07
media: ccs-pll: Remove parallel bus support
Sakari Ailus
2
-15
/
+4
2020-12-07
media: ccs-pll: End search if there are no better values available
Sakari Ailus
1
-2
/
+8
2020-12-07
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
3
-188
/
+209
2020-12-07
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs: Fix return value from probe
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs: avoid printing an uninitialized variable
Arnd Bergmann
1
-2
/
+1
2020-12-07
media: i2c: fix an uninitialized error code
Arnd Bergmann
1
-1
/
+3
2020-12-03
media: ccs: Use all regulators
Sakari Ailus
2
-8
/
+24
2020-12-03
media: ccs: Remove unnecessary delays from power-up sequence
Sakari Ailus
1
-2
/
+0
2020-12-03
media: ccs: Use longer pre-I²C sleep for CCS compliant devices
Sakari Ailus
1
-1
/
+6
2020-12-03
media: ccs: Wrap long lines, unwrap short ones
Sakari Ailus
1
-27
/
+18
2020-12-03
media: ccs: Clean up runtime PM usage
Sakari Ailus
1
-5
/
+2
2020-12-03
media: ccs: Use static data read-only registers
Sakari Ailus
1
-4
/
+60
2020-12-03
media: ccs: Add support for manufacturer regs from sensor and module files
Sakari Ailus
3
-22
/
+97
2020-12-03
media: ccs: Allow range in between I²C retries
Sakari Ailus
1
-2
/
+2
2020-12-03
media: ccs: Change my e-mail address
Sakari Ailus
8
-11
/
+11
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