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2022-12-21Merge tag 'mailbox-v6.2' of ↵Linus Torvalds7-57/+118
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - qcom: enable sc8280xp, sm8550 and sm4250 support - ti: default to ARCH_K3 for msg manager - mediatek: - add mt8188 and mt8186 support - request irq only after got ready - zynq-ipi: fix error handling after device_register - mpfs: check sys-con status - rockchip: simplify by using device_get_match_data * tag 'mailbox-v6.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: qcom-ipcc: Add compatible for SM8550 mailbox: mtk-cmdq: Do not request irq until we are ready mailbox: zynq-ipi: fix error handling while device_register() fails mailbox: mtk-cmdq-mailbox: Use platform data directly instead of copying mailbox: arm_mhuv2: Fix return value check in mhuv2_probe() dt-bindings: mailbox: mediatek,gce-mailbox: add mt8188 compatible name dt-bindings: mailbox: add GCE header file for mt8188 mailbox: mpfs: read the system controller's status mailbox: mtk-cmdq: add MT8186 support mailbox: mtk-cmdq: add gce ddr enable support flow mailbox: mtk-cmdq: add gce software ddr enable private data mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number mailbox: rockchip: Use device_get_match_data() to simplify the code dt-bindings: mailbox: qcom-ipcc: Add sc8280xp compatible mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg manager mailbox: qcom-apcs-ipc: Add SM4250 APCS IPC support dt-bindings: mailbox: qcom: Add SM4250 APCS compatible
2022-12-19mailbox: mtk-cmdq: Do not request irq until we are readyRicardo Ribalda1-6/+7
If the system comes from kexec() the peripheral might trigger an IRQ befoe we are ready for it. Triggering a crash due to an access to invalid memory. Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: zynq-ipi: fix error handling while device_register() failsYang Yingliang1-1/+3
If device_register() fails, it has two issues: 1. The name allocated by dev_set_name() is leaked. 2. The parent of device is not NULL, device_unregister() is called in zynqmp_ipi_free_mboxes(), it will lead a kernel crash because of removing not added device. Call put_device() to give up the reference, so the name is freed in kobject_cleanup(). Add device registered check in zynqmp_ipi_free_mboxes() to avoid null-ptr-deref. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mtk-cmdq-mailbox: Use platform data directly instead of copyingAngeloGioacchino Del Regno1-49/+39
Copying platform data to struct cmdq serves to no purpose, as that data is never modified during runtime: it's worth at this point storing a pointer to gce_plat in gce and. Remove all duplicated `struct gce_plat` members from `struct gce` and reuse the platform data across the driver to save some memory. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: arm_mhuv2: Fix return value check in mhuv2_probe()Yang Yingliang1-2/+2
If devm_of_iomap() fails, it returns ERR_PTR() and never return NULL, so replace NULL pointer check with IS_ERR() to fix this problem. Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mpfs: read the system controller's statusConor Dooley1-3/+28
Some services explicitly return an error code in their response, but others rely on the system controller to set a status in its status register. The meaning of the bits varies based on what service is requested, so pass it back up to the driver that requested the service in the first place. The field in the message struct already existed, but was unused until now. If the system controller is busy, in which case we should never actually be in the interrupt handler, or if the service fails the mailbox itself should not be read. Callers should check the status before operating on the response. There's an existing, but unused, #define for the mailbox mask - but it was incorrect. It was doing a GENMASK_ULL(32, 16) which should've just been a GENMASK(31, 16), so fix that up and start using it. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mtk-cmdq: add MT8186 supportYongqiang Niu1-0/+9
add MT8186 cmdq support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mtk-cmdq: add gce ddr enable support flowYongqiang Niu1-0/+22
add gce ddr enable control flow when gce suspend/resume when all cmdq instruction task has been processed done, we need set this gce ddr enable to disable status to tell cmdq hardware gce there is none task need process, and the hardware can go into idle mode and no access ddr anymore, then the spm can go into suspend. the original issue is gce still access ddr when cmdq suspend function call, but there is no task run. so, we need control gce access ddr with this flow. when cmdq suspend function, there is no task need process, we can disable gce access ddr, to make sure system go into suspend success. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mtk-cmdq: add gce software ddr enable private dataYongqiang Niu1-1/+11
if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of numberYongqiang Niu1-1/+3
Use GCE_CTRL_BY_SW definition instead of number Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: rockchip: Use device_get_match_data() to simplify the codeye xingchen1-3/+1
Directly get the match data with device_get_match_data(). Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg managerNicolas Frayer1-0/+1
Defaulting the build to ARCH_K3 for the TI message manager driver. Signed-off-by: Nicolas Frayer <nfrayer@baylibre.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-19mailbox: qcom-apcs-ipc: Add SM4250 APCS IPC supportBhupesh Sharma1-0/+1
Enable SM4250 APCS IPC support by adding the compatible. It reuses msm8994_apcs_data. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-12-13Merge tag 'acpi-6.2-rc1' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI and PNP updates from Rafael Wysocki: "These include new code (for instance, support for the FFH address space type and support for new firmware data structures in ACPICA), some new quirks (mostly related to backlight handling and I2C enumeration), a number of fixes and a fair amount of cleanups all over. Specifics: - Update the ACPICA code in the kernel to the 20221020 upstream version and fix a couple of issues in it: - Make acpi_ex_load_op() match upstream implementation (Rafael Wysocki) - Add support for loong_arch-specific APICs in MADT (Huacai Chen) - Add support for fixed PCIe wake event (Huacai Chen) - Add EBDA pointer sanity checks (Vit Kabele) - Avoid accessing VGA memory when EBDA < 1KiB (Vit Kabele) - Add CCEL table support to both compiler/disassembler (Kuppuswamy Sathyanarayanan) - Add a couple of new UUIDs to the known UUID list (Bob Moore) - Add support for FFH Opregion special context data (Sudeep Holla) - Improve warning message for "invalid ACPI name" (Bob Moore) - Add support for CXL 3.0 structures (CXIMS & RDPAS) in the CEDT table (Alison Schofield) - Prepare IORT support for revision E.e (Robin Murphy) - Finish support for the CDAT table (Bob Moore) - Fix error code path in acpi_ds_call_control_method() (Rafael Wysocki) - Fix use-after-free in acpi_ut_copy_ipackage_to_ipackage() (Li Zetao) - Update the version of the ACPICA code in the kernel (Bob Moore) - Use ZERO_PAGE(0) instead of empty_zero_page in the ACPI device enumeration code (Giulio Benetti) - Change the return type of the ACPI driver remove callback to void and update its users accordingly (Dawei Li) - Add general support for FFH address space type and implement the low- level part of it for ARM64 (Sudeep Holla) - Fix stale comments in the ACPI tables parsing code and make it print more messages related to MADT (Hanjun Guo, Huacai Chen) - Replace invocations of generic library functions with more kernel- specific counterparts in the ACPI sysfs interface (Christophe JAILLET, Xu Panda) - Print full name paths of ACPI power resource objects during enumeration (Kane Chen) - Eliminate a compiler warning regarding a missing function prototype in the ACPI power management code (Sudeep Holla) - Fix and clean up the ACPI processor driver (Rafael Wysocki, Li Zhong, Colin Ian King, Sudeep Holla) - Add quirk for the HP Pavilion Gaming 15-cx0041ur to the ACPI EC driver (Mia Kanashi) - Add some mew ACPI backlight handling quirks and update some existing ones (Hans de Goede) - Make the ACPI backlight driver prefer the native backlight control over vendor backlight control when possible (Hans de Goede) - Drop unsetting ACPI APEI driver data on remove (Uwe Kleine-König) - Use xchg_release() instead of cmpxchg() for updating new GHES cache slots (Ard Biesheuvel) - Clean up the ACPI APEI code (Sudeep Holla, Christophe JAILLET, Jay Lu) - Add new I2C device enumeration quirks for Medion Lifetab S10346 and Lenovo Yoga Tab 3 Pro (YT3-X90F) (Hans de Goede) - Make the ACPI battery driver notify user space about adding new battery hooks and removing the existing ones (Armin Wolf) - Modify the pfr_update and pfr_telemetry drivers to use ACPI_FREE() for freeing acpi_object structures to help diagnostics (Wang ShaoBo) - Make the ACPI fan driver use sysfs_emit_at() in its sysfs interface code (ye xingchen) - Fix the _FIF package extraction failure handling in the ACPI fan driver (Hanjun Guo) - Fix the PCC mailbox handling error code path (Huisong Li) - Avoid using PCC Opregions if there is no platform interrupt allocated for this purpose (Huisong Li) - Use sysfs_emit() instead of scnprintf() in the ACPI PAD driver and CPPC library (ye xingchen) - Fix some kernel-doc issues in the ACPI GSI processing code (Xiongfeng Wang) - Fix name memory leak in pnp_alloc_dev() (Yang Yingliang) - Do not disable PNP devices on suspend when they cannot be re-enabled on resume (Hans de Goede) - Clean up the ACPI thermal driver a bit (Rafael Wysocki)" * tag 'acpi-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (67 commits) ACPI: x86: Add skip i2c clients quirk for Medion Lifetab S10346 ACPI: APEI: EINJ: Refactor available_error_type_show() ACPI: APEI: EINJ: Fix formatting errors ACPI: processor: perflib: Adjust acpi_processor_notify_smm() return value ACPI: processor: perflib: Rearrange acpi_processor_notify_smm() ACPI: processor: perflib: Rearrange unregistration routine ACPI: processor: perflib: Drop redundant parentheses ACPI: processor: perflib: Adjust white space ACPI: processor: idle: Drop unnecessary statements and parens ACPI: thermal: Adjust critical.flags.valid check ACPI: fan: Convert to use sysfs_emit_at() API ACPICA: Fix use-after-free in acpi_ut_copy_ipackage_to_ipackage() ACPI: battery: Call power_supply_changed() when adding hooks ACPI: use sysfs_emit() instead of scnprintf() ACPI: x86: Add skip i2c clients quirk for Lenovo Yoga Tab 3 Pro (YT3-X90F) ACPI: APEI: Remove a useless include PNP: Do not disable devices on suspend when they cannot be re-enabled on resume ACPI: processor: Silence missing prototype warnings ACPI: processor_idle: Silence missing prototype warnings ACPI: PM: Silence missing prototype warning ...
2022-11-23mailbox: pcc: Reset pcc_chan_count to zero in case of PCC probe failureHuisong Li1-0/+1
Currently, 'pcc_chan_count' is remains set to a non-zero value if PCC subspaces are parsed successfully but something else fail later during the initial PCC probing phase. This will result in pcc_mbox_request_channel trying to access the resources that are not initialised or allocated and may end up in a system crash. Reset pcc_chan_count to 0 when the PCC probe fails in order to prevent the possible issue as described above. Fixes: ce028702ddbc ("mailbox: pcc: Move bulk of PCCT parsing into pcc_mbox_probe") Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-11-17genirq: Get rid of GENERIC_MSI_IRQ_DOMAINThomas Gleixner1-1/+1
Adjust to reality and remove another layer of pointless Kconfig indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve all purposes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20221111122014.524842979@linutronix.de
2022-10-06mailbox: qcom-ipcc: flag IRQ NO_THREADEric Chanudet1-1/+2
PREEMPT_RT forces qcom-ipcc's handler to be threaded with interrupts enabled, which triggers a warning in __handle_irq_event_percpu(): irq 173 handler irq_default_primary_handler+0x0/0x10 enabled interrupts WARNING: CPU: 0 PID: 77 at kernel/irq/handle.c:161 __handle_irq_event_percpu+0x4c4/0x4d0 Mark it IRQF_NO_THREAD to avoid running the handler in a threaded context with threadirqs or PREEMPT_RT enabled. Signed-off-by: Eric Chanudet <echanude@redhat.com> Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: pcc: Fix spelling mistake "Plaform" -> "Platform"Colin Ian King1-1/+1
There is a spelling mistake in a pr_err message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sgJack Wang1-4/+4
dma_map_sg return 0 on error, fix the error check, and return -EIO to caller. Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") Signed-off-by: Jack Wang <jinpu.wang@ionos.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock supportRobert Marko1-1/+1
IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018. IPQ6018 and IPQ8074 use the same controller and driver, so just utilize IPQ6018 match data for IPQ8074. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: mpfs: account for mbox offsets while sendingConor Dooley1-4/+3
The mailbox offset is not only used for receiving messages, but it is also used by messages sent to the system controller by Linux that have a payload, such as the "digital signature service". It is also overloaded by certain other services (reprogramming of the FPGA fabric, see Link:) to have a meaning other than the offset the system controller should read from. When the driver was written, no such services of the latter type were in use & those of the former used an offset of zero so this has gone un-noticed. Link: https://www.microsemi.com/document-portal/doc_download/1245815-polarfire-fpga-and-polarfire-soc-fpga-system-services-user-guide # Section 5.2 Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: mpfs: fix handling of the reg propertyConor Dooley1-10/+14
The "data" region of the PolarFire SoC's system controller mailbox is not one continuous register space - the system controller's QSPI sits between the control and data registers. Split the "data" reg into two parts: "data" & "control". Optionally get the "data" register address from the 3rd reg property in the devicetree & fall back to using the old base + MAILBOX_REG_OFFSET that the current code uses. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-06mailbox: imx: fix RST channel supportPeng Fan1-5/+5
Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated to include the CR register. Add the missed CR register to xcr array. Fixes: 82ab513baed5 ("mailbox: imx: support RST channel") Reported-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15mailbox: apple: Implement poll_data() operationHector Martin1-3/+33
This allows clients running in atomic context to poll for messages to arrive. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15mailbox: apple: Implement flush() operationHector Martin1-0/+27
This allows clients to use the atomic-safe mailbox API style. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-08Merge tag 'mailbox-v5.20' of ↵Linus Torvalds2-17/+34
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - mtk: - use rx_callback instead of cmdq_task_cb - qcom: - add syscon const - add SM6375 compatible - imx: - enable RST channel - clear pending irqs * tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: clear pending interrupts dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible mailbox: imx: support RST channel dt-bindings: mailbox: imx-mu: add RST channel dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb
2022-08-03mailbox: imx: clear pending interruptsPeng Fan1-0/+11
During MU initialization, there maybe pending GSR and RSR pending interrupt, clear them to avoid unexpected kernel dump when requesting mailbox channel Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-02mailbox: imx: support RST channelPeng Fan1-6/+23
i.MX generic MU supports MU-A/B reset feature. When stop/start remotecore, MU is not reset. So when Linux stop remotecore, the MU-B side BCR may contain valid configuration, because MU-B is not reset. So when linux start Mcore again and notify Mcore, Mcore is not ready to handle MU interrupt and cause issues. So need reset MU when stop Mcore. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-02mailbox: mtk-cmdq: Remove proprietary cmdq_task_cbChun-Kuang Hu1-11/+0
rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. Client driver has changed to use standard rx_callback, so remove proprietary cmdq_task_cb. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE ↵Thomas Gleixner1-12/+2
(part 2) Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-05-24mailbox: qcom-ipcc: Fix -Wunused-function with CONFIG_PM_SLEEP=nNathan Chancellor1-1/+1
When CONFIG_PM_SLEEP is not set, there is a warning that qcom_ipcc_pm_resume() is unused: drivers/mailbox/qcom-ipcc.c:258:12: error: 'qcom_ipcc_pm_resume' defined but not used [-Werror=unused-function] 258 | static int qcom_ipcc_pm_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Commit 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones") reworked the PM_OPS macros to avoid this problem. Use NOIRQ_SYSTEM_SLEEP_PM_OPS directly so that qcom_ipcc_pm_resume() always appears to be used to the compiler, even though it will be dead code eliminated in the !CONFIG_PM_SLEEP case. Fixes: c25f77899753 ("mailbox: qcom-ipcc: Log the pending interrupt during resume") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-23mailbox: forward the hrtimer if not queued and under a lockBjörn Ardö1-6/+13
This reverts commit c7dacf5b0f32957b24ef29df1207dc2cd8307743, "mailbox: avoid timer start from callback" The previous commit was reverted since it lead to a race that caused the hrtimer to not be started at all. The check for hrtimer_active() in msg_submit() will return true if the callback function txdone_hrtimer() is currently running. This function could return HRTIMER_NORESTART and then the timer will not be restarted, and also msg_submit() will not start the timer. This will lead to a message actually being submitted but no timer will start to check for its compleation. The original fix that added checking hrtimer_active() was added to avoid a warning with hrtimer_forward. Looking in the kernel another solution to avoid this warning is to check hrtimer_is_queued() before calling hrtimer_forward_now() instead. This however requires a lock so the timer is not started by msg_submit() inbetween this check and the hrtimer_forward() call. Fixes: c7dacf5b0f32 ("mailbox: avoid timer start from callback") Signed-off-by: Björn Ardö <bjorn.ardo@axis.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: qcom-ipcc: Log the pending interrupt during resumePrasad Sodagudi1-0/+23
Enable logging of the pending interrupt that triggered device wakeup. This logging information helps to debug IRQs that cause periodic device wakeups by printing the detailed information of pending IPCC interrupts. Scenario: Device wakeup caused by Modem crash Logs: qcom-ipcc mailbox: virq: 182 triggered client-id: 2; signal-id: 2 From the IPCC bindings it can further be understood that the client here is IPCC_CLIENT_MPSS and the signal was IPCC_MPROC_SIGNAL_SMP2P. Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: pcc: Fix an invalid-load caught by the address sanitizerMario Limonciello1-1/+1
`pcc_mailbox_probe` doesn't initialize all memory that has been allocated before the first time that one of it's members `txdone_irq` may be accessed. This leads to a an invalid load any time that this member is accessed: [ 2.429769] UBSAN: invalid-load in drivers/mailbox/pcc.c:684:22 [ 2.430324] UBSAN: invalid-load in drivers/mailbox/mailbox.c:486:12 [ 4.276782] UBSAN: invalid-load in drivers/acpi/cppc_acpi.c:314:45 Link: https://bugzilla.kernel.org/show_bug.cgi?id=215587 Fixes: ce028702ddbc ("mailbox: pcc: Move bulk of PCCT parsing into pcc_mbox_probe") Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: correct kerneldocKrzysztof Kozlowski3-3/+5
Correct kerneldoc warnings like: drivers/mailbox/arm_mhu_db.c:47: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/mailbox/qcom-ipcc.c:58: warning: Function parameter or member 'num_chans' not described in 'qcom_ipcc' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: omap: using pm_runtime_resume_and_get to simplify the coderan jianping1-4/+2
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ran jianping <ran.jianping@zte.com.cn> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox:imx: using pm_runtime_resume_and_getran jianping1-4/+2
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ran jianping <ran.jianping@zte.com.cn> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: mediatek: support mt8186 adsp mailboxTinghan Shen1-0/+8
Add support of mt8186 adsp mailbox. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: tegra-hsp: Add 128-bit shared mailbox supportKartik1-3/+74
Add support for 128-bit shared mailboxes found on Tegra234 chips. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: tegra-hsp: Add tegra_hsp_sm_opsKartik1-27/+47
This patch introduces tegra_hsp_sm_ops to abstract send & receive API's for shared mailboxes. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: remove an unneeded NULL check on list iteratorXiaomeng Tong1-1/+1
The list iterator is always non-NULL so it doesn't need to be checked. Thus just remove the unnecessary NULL check. Signed-off-by: Xiaomeng Tong <xiam0nd.tong@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21mailbox: imx: remove redundant initializerTom Rix1-1/+0
Smatch reports this issue imx-mailbox.c:887:10: warning: Initializer entry defined twice imx-mailbox.c:889:10: also defined here .rxdb = imx_mu_generic_rxdb, Is listed twice, so remove one. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspendDave Gerlach1-2/+91
During the system suspend path we must set all queues to operate in polled mode as it is possible for any protocol built using this mailbox, such as TISCI, to require communication during the no irq phase of suspend, and we cannot rely on interrupts there. Polled mode is implemented by allowing the mailbox user to define an RX channel as part of the message that is sent which is what gets polled for a response. If polled mode is enabled, this will immediately be polled for a response at the end of the mailbox send_data op before returning success for the data send or timing out if no response is received. Finally, to ensure polled mode is always enabled during system suspend, iterate through all queues to set RX queues to polled mode during system suspend and disable polled mode for all in the resume handler. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: ti-msgmgr: Refactor message read during interrupt handlerDave Gerlach1-39/+49
Refactor the portion of code that actually reads received messages from a queue into its own function, ti_msgmgr_queue_rx_data, that is called by the interrupt handler instead of reading directly from the handler. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: support i.MX93 S401 MUPeng Fan1-0/+12
Add i.MX93 S401 MU cfg Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: support dual interruptsPeng Fan1-15/+30
i.MX93 S401 MU support two interrupts: tx empty and rx full. - Introduce a new flag IMX_MU_V2_IRQ for the dual interrupt case - Update Copyright Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: extend irq to an arrayPeng Fan1-7/+7
To i.MX93 S401 MU, there are two interrupts: rx full and tx empty. So extend irq to an array to prepare i.MX93 S401 MU support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: add i.MX8 SECO MU supportFranck LENORMAND1-1/+212
i.MX8/8X SECO firmware IPC is an implementation of passing messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX, four RX and a TXDB to support IPC to SECO firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SECO MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg of any size, limited by hardcoded value of 30. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: introduce rxdb callbackPeng Fan1-3/+17
Add a rxdb callback to prepare for i.MX8 SECO MU rxdb which has a different logic. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-03-13mailbox: imx: enlarge timeout while reading/writing messages to SCFWRanjani Vaidyanathan1-2/+3
Mailbox driver needs to wait and read all the words in response to a SCFW API call, else the protocol gets messed up and results in kernel hang. When the responses are longer than 3 words its possible that SCFW will take some time to fill up the rest of the words in the MU, a timeout of 100us is arbritrary and too short. While waiting for Linux to consume the first 3 words of the response SCFW can be busy doing other stuff and hence Linux needs to wait for the rest of the words. Similar restriction applies when writing messages that are longer than 3 words. This patch increases the timeout to 5secs while waiting for response or writing long messages to SCFW. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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