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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
irqchip
/
irq-sifive-plic.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-06-10
irqchip: Bulk conversion to generic_handle_domain_irq()
Marc Zyngier
1
-5
/
+3
2021-04-07
irqchip/sifive-plic: Mark two global variables __ro_after_init
Jisheng Zhang
1
-2
/
+2
2020-11-01
irqchip/sifive-plic: Fix chip_data access within a hierarchy
Greentime Hu
1
-4
/
+4
2020-10-25
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
Greentime Hu
1
-1
/
+1
2020-06-10
irqchip: RISC-V per-HART local interrupt controller driver
Anup Patel
1
-9
/
+23
2020-06-10
RISC-V: Rename and move plic_find_hart_id() to arch directory
Anup Patel
1
-15
/
+1
2020-05-25
irqchip/sifive-plic: Improve boot prints for multiple PLIC instances
Anup Patel
1
-2
/
+2
2020-05-25
irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present
Anup Patel
1
-2
/
+12
2020-05-25
irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
Anup Patel
1
-0
/
+3
2020-05-18
irqchip/sifive-plic: Remove incorrect requirement about number of irq contexts
Wesley W. Terpstra
1
-2
/
+0
2020-04-17
irqchip/sifive-plic: Fix maximum priority threshold value
Atish Patra
1
-1
/
+1
2020-03-16
irqchip/sifive-plic: Add support for multiple PLICs
Atish Patra
1
-30
/
+51
2020-03-16
irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline
Atish Patra
1
-4
/
+34
2020-01-24
Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...
Thomas Gleixner
1
-4
/
+26
2020-01-20
irqchip/sifive-plic: Support irq domain hierarchy
Yash Shah
1
-4
/
+26
2020-01-05
riscv: prefix IRQ_ macro names with an RV_ namespace
Paul Walmsley
1
-1
/
+1
2019-11-05
riscv: abstract out CSR names for supervisor vs machine mode
Christoph Hellwig
1
-4
/
+7
2019-10-25
Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...
Thomas Gleixner
1
-2
/
+2
2019-10-25
irqchip/sifive-plic: Skip contexts except supervisor in plic_init()
Alan Mikhak
1
-2
/
+2
2019-10-14
Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...
Thomas Gleixner
1
-14
/
+15
2019-09-18
irqchip/sifive-plic: Switch to fasteoi flow
Marc Zyngier
1
-14
/
+15
2019-09-05
irqchip/sifive-plic: set max threshold for ignored handlers
Christoph Hellwig
1
-2
/
+10
2019-02-21
irqchip/sifive-plic: Implement irq_set_affinity() for SMP host
Anup Patel
1
-6
/
+39
2019-02-21
irqchip/sifive-plic: Differentiate between PLIC handler and context
Anup Patel
1
-8
/
+8
2019-02-21
irqchip/sifive-plic: Add warning in plic_init() if handler already present
Anup Patel
1
-0
/
+5
2019-02-21
irqchip/sifive-plic: Pre-compute context hart base and enable base
Anup Patel
1
-26
/
+21
2019-02-14
irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.
Atish Patra
1
-0
/
+5
2018-10-23
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
1
-3
/
+5
2018-10-23
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
1
-1
/
+1
2018-08-13
irqchip: add a SiFive PLIC driver
Christoph Hellwig
1
-0
/
+260