summaryrefslogtreecommitdiff
path: root/drivers/irqchip/irq-sifive-plic.c
AgeCommit message (Expand)AuthorFilesLines
2022-11-28irqchip/sifive-plic: Support wake IRQsSamuel Holland1-2/+4
2022-08-07Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-3/+4
2022-07-20riscv: cpu: Add 64bit hartid support on RV64Sunil V L1-3/+4
2022-07-10irqchip/sifive-plic: Separate the enable and mask operationsSamuel Holland1-21/+34
2022-07-10irqchip/sifive-plic: Make better use of the effective affinity maskSamuel Holland1-18/+9
2022-07-01irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handlingSamuel Holland1-1/+1
2022-07-01irqchip/sifive-plic: Add support for Renesas RZ/Five SoCLad Prabhakar1-4/+74
2022-03-14Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz...Thomas Gleixner1-12/+26
2022-03-02irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel1-5/+19
2022-03-02irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel1-7/+7
2022-02-02irqchip/sifive-plic: Add missing thead,c900-plic match stringGuo Ren1-0/+1
2021-11-12irqchip/sifive-plic: Fixup EOI failed when maskedGuo Ren1-1/+7
2021-06-10irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier1-5/+3
2021-04-07irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang1-2/+2
2020-11-01irqchip/sifive-plic: Fix chip_data access within a hierarchyGreentime Hu1-4/+4
2020-10-25irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGreentime Hu1-1/+1
2020-06-10irqchip: RISC-V per-HART local interrupt controller driverAnup Patel1-9/+23
2020-06-10RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel1-15/+1
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel1-2/+2
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel1-2/+12
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel1-0/+3
2020-05-18irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsWesley W. Terpstra1-2/+0
2020-04-17irqchip/sifive-plic: Fix maximum priority threshold valueAtish Patra1-1/+1
2020-03-16irqchip/sifive-plic: Add support for multiple PLICsAtish Patra1-30/+51
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra1-4/+34
2020-01-24Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...Thomas Gleixner1-4/+26
2020-01-20irqchip/sifive-plic: Support irq domain hierarchyYash Shah1-4/+26
2020-01-05riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley1-1/+1
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-4/+7
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner1-2/+2
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak1-2/+2
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...Thomas Gleixner1-14/+15
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier1-14/+15
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig1-2/+10
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostAnup Patel1-6/+39
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextAnup Patel1-8/+8
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentAnup Patel1-0/+5
2019-02-21irqchip/sifive-plic: Pre-compute context hart base and enable baseAnup Patel1-26/+21
2019-02-14irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Atish Patra1-0/+5
2018-10-23RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-3/+5
2018-10-23RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt1-1/+1
2018-08-13irqchip: add a SiFive PLIC driverChristoph Hellwig1-0/+260
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-28 03:49:46 +0300