starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-10-26	irq: remove handle_domain_{irq,nmi}()	Mark Rutland	1	-1/+1
2021-04-07	irqchip/hisi: Use the correct HiSilicon copyright	Hao Fang	1	-2/+2
2020-12-11	irqchip/hip04: Make IPIs use handle_percpu_devid_irq()	Valentin Schneider	1	-5/+1
2020-09-17	irqchip/hip04: Configure IPIs as standard interrupts	Marc Zyngier	1	-49/+40
2019-08-20	irqchip/gic: Prepare for more than 16 PPIs	Marc Zyngier	1	-1/+1
2019-08-20	irqchip/gic: Rework gic_configure_irq to take the full ICFGR base	Marc Zyngier	1	-1/+6
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	Thomas Gleixner	1	-4/+1
2017-08-18	irqchip/hip04: Report that effective affinity is a single target	Marc Zyngier	1	-0/+3
2016-12-25	cpu/hotplug: Cleanup state names	Thomas Gleixner	1	-1/+1
2016-07-14	irqchip/hip04: Convert to hotplug state machine	Richard Cochran	1	-20/+5
2016-05-28	remove lots of IS_ERR_VALUE abuses	Arnd Bergmann	1	-1/+1
2015-10-13	irqdomain: Use irq_domain_get_of_node() instead of direct field access	Marc Zyngier	1	-1/+1
2015-09-16	irqchip: Kill off set_irq_flags usage	Rob Herring	1	-2/+2
2015-07-27	irqchip/gic: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND	Sudeep Holla	1	-1/+3
2015-07-12	irqchip: Prepare for local stub header removal	Joel Porquet	1	-1/+1
2015-06-05	irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED	Sudeep Holla	1	-0/+1
2015-01-26	irqchip: gic: Allow interrupt level to be set for PPIs	Liviu Dudau	1	-3/+6
2015-01-07	irqchip: hip04: Initialize hip04_cpu_map to 0xffff	Wang Long	1	-1/+1
2014-11-02	irqchip: hip04: Convert to handle_domain_irq	Marc Zyngier	1	-2/+1
2014-08-20	irqchip: hip04: Enable Hisilicon HiP04 interrupt controller	Haojian Zhuang	1	-0/+424