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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
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beaglev-5.13.y
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fedora-vic-7100_5.10.6
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starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
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visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
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visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
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visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
irqchip
/
irq-brcmstb-l2.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-10-19
irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller
Doug Berger
1
-22
/
+64
2017-10-19
irqchip/brcmstb-l2: Abstract register accesses
Doug Berger
1
-9
/
+20
2017-10-19
irqchip/brcmstb-l2: Remove some processing from the handler
Doug Berger
1
-24
/
+48
2017-08-07
irqchip: brcmstb-l2: Define an irq_pm_shutdown function
Florian Fainelli
1
-0
/
+1
2016-10-12
treewide: remove redundant #include <linux/kconfig.h>
Masahiro Yamada
1
-1
/
+0
2016-06-13
irqchip/brcmstb-l2: Make of probe function static
Ben Dooks
1
-2
/
+2
2015-09-16
genirq: Remove irq argument from irq flow handlers
Thomas Gleixner
1
-4
/
+3
2015-07-16
irqchip/brcmstb-l2: Prepare brcmstb_l2_intc_irq_handle for irq argument removal
Thomas Gleixner
1
-1
/
+3
2015-07-12
irqchip/brcmstb-l2: Consolidate chained IRQ handler install/remove
Thomas Gleixner
1
-2
/
+2
2015-07-12
irqchip: Prepare for local stub header removal
Joel Porquet
1
-2
/
+0
2015-04-01
IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time
Brian Norris
1
-3
/
+6
2014-12-10
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...
Linus Torvalds
1
-15
/
+26
2014-11-26
irqchip: brcmstb-l2: Fix error handling of irq_of_parse_and_map
Dmitry Torokhov
1
-2
/
+2
2014-11-09
irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel}
Kevin Cernekee
1
-12
/
+22
2014-11-09
irqchip: brcmstb-l2: Eliminate dependency on ARM code
Kevin Cernekee
1
-3
/
+4
2014-06-21
irqchip: brcmstb-l2: Level-2 interrupts are edge sensitive
Florian Fainelli
1
-1
/
+1
2014-05-27
irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller
Florian Fainelli
1
-0
/
+202