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The driver forgets to enable bus mastering for the PCI device.
Fix this.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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This adds Intel(R) Trace Hub PCI ID for Denverton SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
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This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Laurent Fert <laurent.fert@intel.com>
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Already during the subdevice initialization time, devices will need
to reference Intel TH controller descriptor structure.
This patch moves setting the drvdata from the pci glue to intel_th
core, before subdevices are populated.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This adds Intel(R) Trace Hub PCI ID for Broxton SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This patch adds basic support for PCI-based Intel TH devices. It requests
2 bars (configuration registers for the subdevices and STH channel MMIO
region) and calls into Intel TH core code to create the bus with subdevices
etc.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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