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2021-03-24drm/i915: Ensure we hold the object mutex in pin correctly.Maarten Lankhorst3-2/+14
Currently we have a lot of places where we hold the gem object lock, but haven't yet been converted to the ww dance. Complain loudly about those places. i915_vma_pin shouldn't have the obj lock held, so we can do a ww dance, while i915_vma_pin_ww should. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> #irc Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323155059.628690-6-maarten.lankhorst@linux.intel.com
2021-03-24drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2.Maarten Lankhorst1-11/+24
i915_vma_pin may fail with -EDEADLK when we start locking page tables, so ensure we handle this correctly. Changes since v1: - Drop -EDEADLK todo, this commit handles it. - Change eb_pin_vma from sort-of-bool + -EDEADLK to a proper int. (Matt) Cc: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323155059.628690-5-maarten.lankhorst@linux.intel.com
2021-03-24drm/i915: Move cmd parser pinning to execbufferMaarten Lankhorst8-80/+142
We need to get rid of allocations in the cmd parser, because it needs to be called from a signaling context, first move all pinning to execbuf, where we already hold all locks. Allocate jump_whitelist in the execbuffer, and add annotations around intel_engine_cmd_parser(), to ensure we only call the command parser without allocating any memory, or taking any locks we're not supposed to. Because i915_gem_object_get_page() may also allocate memory, add a path to i915_gem_object_get_sg() that prevents memory allocations, and walk the sg list manually. It should be similarly fast. This has the added benefit of being able to catch all memory allocation errors before the point of no return, and return -ENOMEM safely to the execbuf submitter. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323155059.628690-4-maarten.lankhorst@linux.intel.com
2021-03-24drm/i915: Pin timeline map after first timeline pin, v4.Maarten Lankhorst5-44/+83
We're starting to require the reservation lock for pinning, so wait until we have that. Update the selftests to handle this correctly, and ensure pin is called in live_hwsp_rollover_user() and mock_hwsp_freelist(). Changes since v1: - Fix NULL + XX arithmatic, use casts. (kbuild) Changes since v2: - Clear entire cacheline when pinning. Changes since v3: - CACHELINE_BYTES -> TIMELINE_SEQNO_BYTES. (jekstrand) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323155059.628690-3-maarten.lankhorst@linux.intel.com
2021-03-24drm/i915: Do not share hwsp across contexts any more, v8.Maarten Lankhorst11-417/+178
Instead of sharing pages with breadcrumbs, give each timeline a single page. This allows unrelated timelines not to share locks any more during command submission. As an additional benefit, seqno wraparound no longer requires i915_vma_pin, which means we no longer need to worry about a potential -EDEADLK at a point where we are ready to submit. Changes since v1: - Fix erroneous i915_vma_acquire that should be a i915_vma_release (ickle). - Extra check for completion in intel_read_hwsp(). Changes since v2: - Fix inconsistent indent in hwsp_alloc() (kbuild) - memset entire cacheline to 0. Changes since v3: - Do same in intel_timeline_reset_seqno(), and clflush for good measure. Changes since v4: - Use refcounting on timeline, instead of relying on i915_active. - Fix waiting on kernel requests. Changes since v5: - Bump amount of slots to maximum (256), for best wraparounds. - Add hwsp_offset to i915_request to fix potential wraparound hang. - Ensure timeline wrap test works with the changes. - Assign hwsp in intel_timeline_read_hwsp() within the rcu lock to fix a hang. Changes since v6: - Rename i915_request_active_offset to i915_request_active_seqno(), and elaborate the function. (tvrtko) Changes since v7: - Move hunk to where it belongs. (jekstrand) - Replace CACHELINE_BYTES with TIMELINE_SEQNO_BYTES. (jekstrand) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@intel.com> #v1 Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323155059.628690-2-maarten.lankhorst@linux.intel.com
2021-03-24drm/tilcdc: fix pixel clock setting warning messageDario Binacchi1-5/+5
The warning message did not printed the LCD pixel clock rate but the LCD clock divisor input rate. As a consequence, the required and real pixel clock rates are now passed to the tilcdc_pclk_diff(). Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Jyri Sarha <jyri.sarha@iki.fi> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jyri Sarha <jyri.sarha@iki.fi> Link: https://patchwork.freedesktop.org/patch/msgid/20210322213337.26667-4-dariobin@libero.it
2021-03-24drm/tilcdc: fix LCD pixel clock settingDario Binacchi1-2/+3
The tilcdc_pclk_diff() compares the requested pixel clock rate to the real one, so passing it clk_rate instead of clk_rate / clkdiv caused it to fail even if the clk_rate was properly set. Adding the real_pclk_rate variable makes the code more readable. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Jyri Sarha <jyri.sarha@iki.fi> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jyri Sarha <jyri.sarha@iki.fi> Link: https://patchwork.freedesktop.org/patch/msgid/20210322213337.26667-3-dariobin@libero.it
2021-03-24drm/tilcdc: rename req_rate to pclk_rateDario Binacchi1-6/+6
The req_rate name is a little misleading, so let's rename to pclk_rate (pixel clock rate). Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Jyri Sarha <jyri.sarha@iki.fi> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jyri Sarha <jyri.sarha@iki.fi> Link: https://patchwork.freedesktop.org/patch/msgid/20210322213337.26667-2-dariobin@libero.it
2021-03-24drm/tilcdc: panel: fix platform_no_drv_owner.cocci warningsYang Li1-1/+0
./drivers/gpu/drm/tilcdc/tilcdc_panel.c:402:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Jyri Sarha <jyri.sarha@iki.fi> Link: https://patchwork.freedesktop.org/patch/msgid/1614762267-98454-1-git-send-email-yang.lee@linux.alibaba.com
2021-03-24i915_vma: Rename vma_lookup to i915_vma_lookupLiam Howlett1-2/+2
Use i915 prefix to avoid name collision with future vma_lookup() in mm. Signed-off-by: Liam R. Howlett <Liam.Howlett@Oracle.com> Reviewed-by: Matthew Wilcox (Oracle) <willy@infradead.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210323134208.3077275-1-Liam.Howlett@Oracle.com
2021-03-24drm/rockchip: Remove unused variableMaxime Ripard1-2/+0
Commit 977697e20b3d ("drm/atomic: Pass the full state to planes atomic disable and update") added the old_state variable instead of what used to be a parameter, but it also removed the sole user of that variable in the vop_plane_atomic_update function leading to an usused variable. Remove it. Fixes: 977697e20b3d ("drm/atomic: Pass the full state to planes atomic disable and update") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210319152920.262035-1-maxime@cerno.tech
2021-03-24drm/i915: Fix the GT fence revocation runtime PM logicImre Deak3-6/+41
To optimize some task deferring it until runtime resume unless someone holds a runtime PM reference (because in this case the task can be done w/o the overhead of runtime resume), we have to use the runtime PM get-if-active logic: If the runtime PM usage count is 0 (and so get-if-in-use would return false) the runtime suspend handler is not necessarily called yet (it could be just pending), so the device is not necessarily powered down, and so the runtime resume handler is not guaranteed to be called. The fence revocation depends on the above deferral, so add a get-if-active helper and use it during fence revocation. v2: - Add code comment explaining the fence reg programming deferral logic to i915_vma_revoke_fence(). (Chris) - Add Cc: stable and Fixes: tags. (Chris) - Fix the function docbook comment. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: <stable@vger.kernel.org> # v4.12+ Fixes: 181df2d458f3 ("drm/i915: Take rpm wakelock for releasing the fence on unbind") Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210322204223.919936-1-imre.deak@intel.com
2021-03-24drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.xAlex Deucher1-2/+1
Commit 098214999c8f added fetching of the AUX_DPHY register values from the vbios, but it also changed the default values in the case when there are no values in the vbios. This causes problems with displays with high refresh rates. To fix this, switch back to the original default value for AUX_DPHY_TX_CONTROL. Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Igor Kravchenko <Igor.Kravchenko@amd.com> Cc: Aric Cyr <Aric.Cyr@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: stable@vger.kernel.org
2021-03-24drm/amdgpu: Add additional Sienna Cichlid PCI IDAlex Deucher1-0/+1
Add new DID. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-03-24drm/amdgpu: Mark Aldebaran HW support as experimentalFelix Kuehling1-3/+3
The HW is not in production yet. Driver support is still in development. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: revert "reserve backup pages for bad page retirment"Christian König4-118/+15
As noted during the review this approach doesn't make sense at all. We should not apply any limitation on the VRAM applications can use inside the kernel. If an application or end user wants to reserve a certain amount of VRAM for bad pages handling we should do this in the upper layer. This reverts commit f89b881c81d9a6481fc17b46b351ca38f5dd6f3a. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: revert "use the new cursor in the VM code"Christian König1-18/+37
We are seeing VM page faults with this. Revert the change until the bugs are fixed. This reverts commit 94ae8dc55790de8979b58428672c8e0b97ee0dae. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbpsAlex Deucher2-2/+4
Move the function protoype to the right header and guard the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available with DCN. Fixes: 8c2f14c36f47ce ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Dillon Varone <dillon.varone@amd.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
2021-03-24drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c:220:65-70: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong1-2/+2
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:721:65-70: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c:1139:67-72: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: Fix memory leakxinhui pan1-1/+3
drm_gem_object_put() should be paired with drm_gem_object_lookup(). All gem objs are saved in fb->base.obj[]. Need put the old first before assign a new obj. Trigger VRAM leak by running command below $ service gdm restart Signed-off-by: xinhui pan <xinhui.pan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24radeon: use kvcalloc for relocs and chunksChen Li1-3/+3
kvmalloc_array + __GFP_ZERO is the same with kvcalloc. As for p->chunks, it will be used in: ``` if (ib_chunk->kdata) memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); ``` If chunks doesn't zero out with __GFP_ZERO, it may point to somewhere else, e.g., ``` Unable to handle kernel paging request at virtual address 0000000000010000 ... pc is at memcpy+0x84/0x250 ra is at radeon_cs_ioctl+0x368/0xb90 [radeon] ``` after allocating chunks with __GFP_KERNEL/kvcalloc, this bug is fixed. Fixes: 3fcb4f01deed ("drm/radeon: Use kvmalloc for CS chunks") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Li <chenli@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: drop extraneous hw_status updateAlex Deucher1-1/+0
We set the same variable a few lines above. Drop the duplicate setting. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Support vertical interrupt 0 for all dcn ASICWayne Lin4-0/+137
[Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix vertical interrupt 0 registering issueWayne Lin1-6/+19
[Why] Find out that when we are registering vertical interrupt0, we get DC_IRQ_SOURCE_INVALID when call dc_interrupt_to_irq_source for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL. After analyzing, it's due to the defined value for DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL is not (DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL + 1). It's not incremental sequence. [How] Use an array to record all vertical interrupt0 SRCID. While registering interrupt, use an incremental index to visit the array to get the right SRCID to register. Also add error handling to avoid potential pointer problem. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/pm: correct the gpu metrics versionEvan Quan1-1/+1
For V1_0 and V1_1, they come with different size. Misuse may cause out of memory access. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu/display: re-enable freesync video patchesNikola Cornij4-35/+349
Since this is a "revert of a revert", the end effect is that freesync video is back to its original state, the way it was before the first revert. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/pm: Use BACO reset arg 0 on XGMI configurationshaoyunl1-1/+1
With arg 1 BACO reset, it will try to reload the SMU FW after reset. This might failed if driver already in a pending reset status during probe period. Arg 0 reset will bring asic back to a clean state and driver will re-init everythign including SMU FW Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: Keep pending_reset valid during smu reset the ASICshaoyunl1-1/+1
SMU internal might need to check this pending_reset setting to decide the reset method Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amdgpu: Enable light SBR in XGMI+passthrough configurationshaoyunl1-4/+5
This is to fix the case where it only enable the light SMU on normal device init. This feature actually need to be enabled after ASIC been reset as well. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix potential memory leakQingqing Zhuo1-0/+9
[Why] vblank_workqueue is never released. [How] Free it upon dm finish. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: add a func to disable accelerated modeYao Wang15-4/+29
[Why] When driver disabled, we driver force the YCbCr420 to RGB, which means some register will be changed, such as RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0 When driver re-enabled, OS will Set Mode YCbCr420 again, which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV should to be 1 again, but dmub fw can’t update the register to 1 due to the mpll is not off [How] Adds an interface to disable accelerated mode bit, which allows DM to decide to call during driver disable/unload scenarios. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Yao Wang1 <Yao.Wang1@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: fix dcn3+ bw validation soc param update sequenceDmytro Laktyushkin5-5/+17
SOC needs to be updated to the WM set A values before validation happens. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: fix dml prefetch validationDmytro Laktyushkin2-0/+2
Incorrect variable used, missing initialization during validation. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: 3.2.127Aric Cyr1-1/+1
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add debug out when viewport too small * use max lb for latency hiding * System black screen hangs on driver load * Fix UBSAN warning for not a valid value for type '_Bool' * Fix for outbox1 ring buffer typecasting issue * Bypass sink detect when there are no eDPs connected * Increase precision for bpp in DSC calculations * Add changes for dsc bpp in 16ths and unify bw calculations * Correct algorithm for reversed gamma * Remove MPC gamut remap logic for DCN30 * Fix typo for helpers function name * Fix secure display lock problems * Fix no previous prototype warning * Separate caps for maximum RGB and YUV plane counts * Add debugfs to control DMUB trace buffer events * [FW Promotion] Release 0.0.56 * DCHUB underflow counter increasing in some scenarios * fix dml prefetch validation * fix dcn3+ bw validation soc param update sequence * add a func to disable accelerated mode * Fix potential memory leak Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: DCHUB underflow counter increasing in some scenariosAric Cyr1-1/+3
[Why] When unplugging a display, the underflow counter can be seen to increase because PSTATE switch is allowed even when some planes are not blanked. [How] Check that all planes are not active instead of all streams before allowing PSTATE change. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: [FW Promotion] Release 0.0.56Anthony Koo1-142/+526
More updates to the comments to better describe the function of different cmds and parameters in the dmub interface. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Add debugfs to control DMUB trace buffer eventsLeo (Hanghong) Ma2-0/+38
[Why] We want to have a debugfs interface to enable or disable DMCUB trace buffer events. [How] Add debugfs interface to enable or disable trace buffer events. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Separate caps for maximum RGB and YUV plane countsAtufa Khan8-0/+16
Not all ASICs have same plane capabilities so need to split them out for proper support handling. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Atufa Khan <Atufa.Khan@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix no previous prototype warningWayne Lin1-1/+1
[Why] Received compiling warning: All warnings (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5574:5: warning: no previous prototype for 'amdgpu_dm_crtc_late_register' [-Wmissing-prototypes] 5574 | int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'dm_update_mst_vcpi_slots_for_dsc': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6405:46: warning: variable 'old_con_state' set but not used [-Wunused-but-set-variable] 6405 | struct drm_connector_state *new_con_state, *old_con_state; | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function 'amdgpu_dm_commit_cursors': drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8006:44: warning: variable 'new_plane_state' set but not used [-Wunused-but-set-variable] 8006 | struct drm_plane_state *old_plane_state, *new_plane_state; | ^~~~~~~~~~~~~~~ vim +/amdgpu_dm_crtc_late_register +5574 drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c 5572 5573 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY > 5574 int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 5575 { 5576 crtc_debugfs_init(crtc); 5577 5578 return 0; 5579 } 5580 #endif 5581 [How] Fix it with declaration as "static" Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix secure display lock problemsWayne Lin2-9/+7
[Why] Find out few locks problems while doing secure display. They are following few parts: 1. crc_rd_work_lock in amdgpu_dm_crtc_handle_crc_window_irq() should also use spin_lock_irqsave instead of spin_lock_irq. 2. In crc_win_update_set(), crc_rd_work_lock should be grabbed after obtaining lock event_lock. Otherwise, will cause deadlock by conflicting the lock order in amdgpu_dm_crtc_handle_crc_window_irq() 3. flush_work() in crc_win_update_set() is no need and will cause deadlock since amdgpu_dm_crtc_notify_ta_to_read() also tries to grab lock crc_rd_work_lock. [How] Fix above problems. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Solomon Chiu <Solomon.Chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix typo for helpers function nameLeo (Hanghong) Ma3-3/+3
[why] Word "helper" was misspelled as "helpes" in dm_helpes_dmub_outbox0_interrupt_control function. [how] Fix the spelling. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Remove MPC gamut remap logic for DCN30Dillon Varone1-32/+2
[Why?] Should only reroute gamut remap to mpc unless 3D LUT is not used and all planes are using the same src->dest. [How?] Remove DCN30 specific logic for rerouting gamut remap to mpc. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Correct algorithm for reversed gammaCalvin Hou1-8/+18
[Why] DCN30 needs to correctly program reversed gamma curve, which DCN20 already has. Also needs to fix a bug that 252-255 values are clipped. [How] Apply two fixes into DCN30. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Calvin Hou <Calvin.Hou@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Acked-by: Vladimir Stempen <Vladimir.Stempen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculationsDillon Varone3-80/+43
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing. [How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Increase precision for bpp in DSC calculationsJun Lei1-0/+1
[Why?] Many DSC variables and related functions use whole bits for bpp. [How?] Change variables and related functions to use 16ths of a bit for bpp. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Bypass sink detect when there are no eDPs connectedJake Wang1-7/+6
[How & Why] Check DC config to determine if there are any eDPs connected. If there are no eDPs connected, bypass sink detect when querying eDP presence. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix for outbox1 ring buffer typecasting issueMeenakshikumar Somasundaram1-1/+1
[WHY] Compiler warning "pointer to integer of different size" reported on outbox1 ring buffer address typecasting. Reported-by: kernel test robot <lkp@intel.com> [HOW] Fixed the issue by typecasting with character pointer. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool'Anson Jacob1-5/+1
[Why] dc_cursor_position do not initialise position.translate_by_source when crtc or plane->state->fb is NULL. UBSAN caught this error in dce110_set_cursor_position, as the value was garbage. [How] Initialise dc_cursor_position structure elements to 0 in handle_cursor_update before calling get_cursor_position. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1471 Reported-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: System black screen hangs on driver loadAric Cyr2-48/+2
This reverts commit dbc43d5fdf48e4e558338fcaef8c9d19521d1c2e as it causes crash on driver load in some scenarios. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-12 15:24:19 +0300