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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
gpu
/
drm
/
tegra
/
dc.c
Age
Commit message (
Expand
)
Author
Files
Lines
2015-01-27
drm/tegra: dc: Store clock setup in atomic state
Thierry Reding
1
-3
/
+68
2015-01-27
drm/tegra: Atomic conversion, phase 3, step 1
Thierry Reding
1
-6
/
+6
2015-01-27
drm/tegra: Atomic conversion, phase 2
Thierry Reding
1
-0
/
+12
2015-01-27
drm/tegra: Atomic conversion, phase 1
Thierry Reding
1
-184
/
+213
2015-01-27
drm/tegra: dc: Do not needlessly deassert reset
Thierry Reding
1
-4
/
+0
2015-01-27
drm/tegra: Remove remnants of the output midlayer
Thierry Reding
1
-52
/
+0
2015-01-27
drm/tegra: rgb: Demidlayer
Thierry Reding
1
-0
/
+24
2015-01-27
drm/tegra: Add tegra_dc_setup_clock() helper
Thierry Reding
1
-0
/
+20
2015-01-27
drm/tegra: output: Make ->setup_clock() optional
Thierry Reding
1
-1
/
+9
2015-01-27
drm/tegra: dc: No longer disable planes at CRTC disable
Thierry Reding
1
-14
/
+0
2015-01-27
drm/tegra: dc: Wait for idle when disabled
Thierry Reding
1
-5
/
+65
2015-01-27
drm/tegra: Stop CRTC at CRTC disable time
Thierry Reding
1
-0
/
+6
2015-01-27
drm/tegra: Use tegra_commit_dc() in output drivers
Thierry Reding
1
-1
/
+1
2015-01-27
drm/tegra: dc: Fix bad irqsave/restore in tegra_dc_finish_page_flip()
Dan Carpenter
1
-2
/
+2
2015-01-27
drm/tegra: dc: Return planar flag for non-YUV modes
Thierry Reding
1
-0
/
+3
2015-01-27
drm/tegra: dc: Describe register copies
Thierry Reding
1
-0
/
+12
2015-01-27
drm/tegra: dc: Initialize border color
Thierry Reding
1
-0
/
+8
2015-01-27
drm/tegra: plane: Use proper possible_crtcs mask
Thierry Reding
1
-1
/
+14
2015-01-27
drm/tegra: Remove redundant zeroing out of memory
Thierry Reding
1
-6
/
+0
2015-01-09
Merge tag 'topic/core-stuff-2014-12-19' of git://anongit.freedesktop.org/drm-...
Dave Airlie
1
-5
/
+0
2014-12-17
drm/tegra: dc: Select root window for event dispatch
Sean Paul
1
-2
/
+22
2014-12-17
drm/tegra: dc: Fix a potential race on page-flip completion
Thierry Reding
1
-3
/
+7
2014-12-17
drm/tegra: dc: Consistently use the same pipe
Thierry Reding
1
-7
/
+7
2014-12-10
drm/tegra: Remove dummy ->load_lut() implementation
Thierry Reding
1
-5
/
+0
2014-12-02
Merge tag 'v3.18-rc7' into drm-next
Dave Airlie
1
-4
/
+4
2014-11-15
Merge tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linu...
Dave Airlie
1
-180
/
+413
2014-11-13
drm/tegra: dc: Universal plane support
Thierry Reding
1
-157
/
+330
2014-11-13
drm/tegra: dc: Registers are 32 bits wide
Thierry Reding
1
-1
/
+1
2014-11-13
drm/tegra: dc: Factor out DC, window and cursor commit
Thierry Reding
1
-24
/
+28
2014-11-13
drm/tegra: Add IOMMU support
Thierry Reding
1
-0
/
+17
2014-11-13
drm/tegra: dc: Add powergate support
Thierry Reding
1
-3
/
+42
2014-11-13
drm/tegra: dc: Add missing call to drm_vblank_on()
Thierry Reding
1
-5
/
+4
2014-11-05
drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.h
Daniel Vetter
1
-0
/
+2
2014-08-04
drm/tegra: add MODULE_DEVICE_TABLEs
Stephen Warren
1
-0
/
+1
2014-08-04
drm/tegra: dc - Reset controller on driver remove
Thierry Reding
1
-0
/
+1
2014-08-04
drm/tegra: Properly align stride for framebuffers
Thierry Reding
1
-0
/
+19
2014-08-04
drm/tegra: Implement more tiling modes
Thierry Reding
1
-15
/
+87
2014-06-06
drm/tegra: Add hardware cursor support
Thierry Reding
1
-0
/
+111
2014-06-06
drm/tegra: Remove host1x drm_bus implementation
Thierry Reding
1
-5
/
+5
2014-06-06
drm/tegra: dc - Compute shift clock divider in output drivers
Thierry Reding
1
-8
/
+5
2014-06-06
drm/tegra: dc - Move around shift clock programming
Thierry Reding
1
-9
/
+10
2014-06-06
drm/tegra: dc - Use proper H/V ref-to-sync values
Thierry Reding
1
-3
/
+2
2014-06-06
drm/tegra: dc - Do not touch power control register
Thierry Reding
1
-4
/
+0
2014-06-06
drm/tegra: dc - Reshuffle code to get rid of prototypes
Thierry Reding
1
-248
/
+248
2014-06-06
drm/tegra: dc - Rename INVERT_V to V_DIRECTION
Thierry Reding
1
-3
/
+3
2014-06-06
drm/tegra: dc - Add YUYV support
Thierry Reding
1
-5
/
+20
2014-04-24
drm/tegra: restrict plane loops to legacy planes
Daniel Vetter
1
-1
/
+1
2014-04-02
drm: Replace crtc fb with primary plane fb (v3)
Matt Roper
1
-8
/
+8
2014-01-23
drm/tegra: Obtain head number from DT
Thierry Reding
1
-2
/
+39
2013-12-20
drm/tegra: Relocate some output-specific code
Thierry Reding
1
-18
/
+0
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