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path: root/drivers/gpu/drm/nouveau/nvkm/engine
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2017-06-16drm/nouveau/disp/gt215: Use supplied HDMI InfoFramesAlastair Bridgewater1-6/+31
Now that we have the InfoFrame data being provided, for the most part, program the hardware to use it. While we're here, and since the functionality will come in handy for supporting 3D stereoscopy, implement setting the Vendor ("generic") InfoFrame. Also don't enable any AVI or Vendor InfoFrame that is not provided, and disable the Vendor InfoFrame when disabling the output. Ignore the Audio InfoFrame: We don't supply it, and altering HDMI audio semantics (for better or worse) on this hardware is out of scope for me at this time. Signed-off-by: Alastair Bridgewater <alastair.bridgewater@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16drm/nouveau/disp/g84-gt200: Use supplied HDMI InfoFramesAlastair Bridgewater1-6/+31
Now that we have the InfoFrame data being provided, for the most part, program the hardware to use it. While we're here, and since the functionality will come in handy for supporting 3D stereoscopy, implement setting the Vendor ("generic"?) InfoFrame. Also don't enable any AVI or Vendor InfoFrame that is not provided, and disable the Vendor InfoFrame when disabling the output. Ignore the Audio InfoFrame: We don't supply it, and altering HDMI audio semantics (for better or worse) on this hardware is out of scope for me at this time. Signed-off-by: Alastair Bridgewater <alastair.bridgewater@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16drm/nouveau/disp: Add mechanism to convert HDMI InfoFrames to hardware formatAlastair Bridgewater3-0/+78
HDMI InfoFrames are passed to NVKM as bags of bytes, but the hardware needs them to be packed into words. Rather than having four (or more) copies of the packing logic introduce a single copy now, in a central place. We currently need these for AVI and Vendor InfoFrames, but we may also expect to need them for Audio InfoFrames at some point. Signed-off-by: Alastair Bridgewater <alastair.bridgewater@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-06-16drm/nouveau/disp/g84-: Extend NVKM HDMI power control method to set InfoFramesAlastair Bridgewater4-4/+32
The nouveau driver, in the Linux 3.7 days, used to try and set the AVI InfoFrame based on the selected display mode. These days, it uses a fixed set of InfoFrames. Start to correct that, by providing a mechanism whereby InfoFrame data may be passed to the NVKM functions that do the actual configuration. At this point, only establish the new parameters and their parsing, don't actually use the data anywhere yet (since it's not supplied anywhere). Signed-off-by: Alastair Bridgewater <alastair.bridgewater@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-05-17drm/nouveau/fifo/gk104-: Silence a locking warningDan Carpenter1-1/+2
Presumably we can never actually hit this return, but static checkers complain that we should unlock before we return. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-29drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engineIlia Mirkin1-0/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-04-06drm/nouveau/gr/gp107: initial supportBen Skeggs8-8/+119
Forked from GP106 implementation. Differences: - 1 PPC/GPC - Slightly different grctx magics Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/core: recognise GP10B chipsetAlexandre Courbot1-0/+24
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/platform: make VDD regulator optionalAlexandre Courbot1-9/+22
GP10B's power is managed by generic PM domains, so it does not require a VDD regulator. Add this option into the chip function structure. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/gr: support for GP10BAlexandre Courbot5-2/+76
GR is similar to GP100, with a few unavailable registers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/fifo: add GP10B supportAlexandre Courbot4-1/+44
GP10B's FIFO is similar to GP100's, but only allows 512 channels. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/secboot: allow to boot multiple falconsAlexandre Courbot1-7/+9
Change the secboot and msgqueue interfaces to take a mask of falcons to reset instead of a single falcon. The GP10B firmware interface requires FECS and GPCCS to be booted in a single firmware command. For firmwares that only support single falcon boot, it is trivial to loop over the mask and boot each falcons individually. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau: initial support (display-only) for GP107Ben Skeggs1-0/+30
Forked from GP106 implementation. Split out from commit enabling secboot/gr support so that it can be added to earlier kernels. Cc: stable@vger.kernel.org [4.10+] Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 oneIlia Mirkin1-1/+1
The NV4A (aka NV44A) is an oddity in the family. It only comes in AGP and PCI varieties, rather than a core PCIE chip with a bridge for AGP/PCI as necessary. As a result, it appears that the MMU is also non-functional. For AGP cards, the vast majority of the NV4A lineup, this worked out since we force AGP cards to use the nv04 mmu. However for PCI variants, this did not work. Switching to the NV04 MMU makes it work like a charm. Thanks to mwk for the suggestion. This should be a no-op for NV4A AGP boards, as they were using it already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70388 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: stable@vger.kernel.org Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/mpeg: mthd returns true on success nowIlia Mirkin2-2/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Fixes: 590801c1a3 ("drm/nouveau/mpeg: remove dependence on namedb/engctx lookup") Cc: stable@vger.kernel.org # v4.3+ Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-17drm/nouveau/secboot: fix NULL pointer dereferenceAlexandre Courbot1-0/+7
The msgqueue pointer validity should be checked by its owner, not by the msgqueue code itself to avoid this situation. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-07drm/nouveau/fb/gf108: split implementation from gf100Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/gp10x: enable secboot and GRAlexandre Courbot1-0/+15
All the bricks are in place for secure boot to be enabled. This in turn makes GR usable so enable them all. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/gr/gp102: initial supportBen Skeggs7-4/+180
Differences from GP100: - 3 PPCs/GPC. - Another random reg to calculate/write. - Attrib CB setup a little different. - PascalB - PascalComputeB Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/core: add SEC2 engineAlexandre Courbot7-0/+146
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/nvdec: add gp102 supportAlexandre Courbot5-2/+98
gp10x' secure boot requires a blob to be run on NVDEC. Expose the falcon through a dummy device. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07drm/nouveau/falcon: delay construction of falcons to oneinit()Alexandre Courbot1-15/+14
Reading registers at device construction time can be harmful, as there is no guarantee the underlying engine will be up, or in its runtime configuration. Defer register reading to the oneinit() hook and update users accordingly. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-23Merge tag 'v4.10-rc8' into drm-nextDave Airlie2-3/+1
Linux 4.10-rc8 Backmerge Linus rc8 to fix some conflicts, but also to avoid pulling it in via a fixes pull from someone.
2017-02-17drm/nouveau/pci/g92: Fix rearmKarol Herbst1-10/+10
704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com> Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
2017-02-17drm/nouveau/fifo/gk104-: preempt recoveryBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: trigger mmu fault before attempting engine recoveryBen Skeggs1-0/+41
Greatly improves the chances of recovering the GPU from a CTXSW_TIMEOUT. Tested with piglit's arb_shader_image_load_store-atomicity, which causes GR to hang in such a way that recovery failed (CTXSW_TIMEOUT continually re-triggers). Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: ACK SCHED_ERROR before attempting CTXSW_TIMEOUT ↵Ben Skeggs1-0/+8
recovery Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: directly use new recovery code for ctxsw timeoutBen Skeggs1-24/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: directly use new recovery code for mmu faultsBen Skeggs3-8/+37
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: reset all engines a killed channel is still active onBen Skeggs1-0/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: refactor recovery codeBen Skeggs1-14/+81
This will serve as a basis for implementing some improvements to how we recover the GPU from channel errors. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: better detection of chid when parsing engine statusBen Skeggs1-1/+19
The previous commit simply changes the interface, but should result in the same behaviour as previously. This commit has been split out from it as it can result in a different channel being selected. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gk104-: separate out engine status parsingBen Skeggs1-13/+46
We'll be wanting to reuse this logic in more places. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo: add an api for initiating channel recoveryBen Skeggs2-0/+13
This will be used by callers outside of fifo interrupt handlers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr/gf100-: implement chsw_load() methodBen Skeggs1-0/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr: implement chsw_load() methodBen Skeggs2-0/+11
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/gf100-: provide notification to user if channel is killedBen Skeggs8-5/+55
There are instances (such as non-recoverable GPU page faults) where NVKM decides that a channel's context is no longer viable, and will be removed from the runlist. This commit notifies the owner of the channel when this happens, so it has the opportunity to take some kind of recovery action instead of hanging. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo/g84-: rename non-stall interrupt eventBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/fifo: tidy up channel creation event codeBen Skeggs3-6/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/pci/g92: Enable changing pcie link speedsKarol Herbst1-1/+1
Tested on a G92, seems to work. Confirmed by 8 mmiotraces. Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/pci: Rename g94 to g92Karol Herbst1-10/+10
Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/core/memory: distinguish between coherent/non-coherent targetsBen Skeggs2-5/+15
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/dma: lookup objects with nvkm_object_search()Ben Skeggs4-53/+21
Custom code is no longer needed here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/dma: use rb_entry()Geliang Tang1-2/+2
To make the code clearer, use rb_entry() instead of container_of() to deal with rbtree. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr/nv50-mcp89: add defines for gr classesBen Skeggs6-32/+44
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr/gf100-: fix ccache error loggingBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/disp/g94: remove unused sor implementationBen Skeggs1-7/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr/gf100: instantiate and reserve GR falconsAlexandre Courbot2-50/+51
Create instances for the FECS and GPCCS falcons and use the init() and fini() hooks to reserve them for as long as GR controls them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr/gf100: split gf100_gr_init_ctxctl()Alexandre Courbot1-97/+115
gf100_gr_init_ctxctl() is basically two different functions (one for use of internal firmware, the other for use of external firmware), but its current layout makes it look more complex than it is. Split it to better reflect that fact. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17drm/nouveau/gr: add fini() hookAlexandre Courbot2-0/+11
Add a fini() hook to the GR engine. This will be used by gf100+ to properly release the FECS and GPCCS falcons. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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